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Original question:

SPI (?) of ADS8353, ADS7853, ADS7253

ADS8353: serial (SPI) communication

Rok Kimovec
Prodigy 50 points
Part Number: ADS8353


Dear Sir/madam,

According to the answer on e2e,  I should use D flip flop on SDO line if I am to use standard SPI peripheral of uC. When I tried communicating ADS8353 with STM32F412 with built in SPI peripheral using CPOL=0, CPHA=1, I have no problems reading frames as they are without any filp flop in between the SDO and MISO pin on uC. I tried communicating with ADC as slow as I could go (125kHz CLK) with long waits in between frames (1us) and as fast as I could go (25MHz CLK, [I know it is out of specs], 200ns CS high) and I saw no difference. Conversion results obtained by uC were as expected in both cases and also readbacks from registers were as stated in the datasheet and I saw no drop of data in either case. On the other hand, when I used SPI decoding function on my oscilloscope, the SDO data is decoded incorectly (shiffted by one bit according to SPI specification) as explained in the linked e2e question on the serial communication.

Could it be that the current setup I am using (ADC mounted on breakout board and placed in breadboard and uC mounted on a nucleo development board and both connected by 10cm of wire) is causing such a time delay that the uC is seeing SDO data shifted such that it is reading it correctly? Is there a possibility that on a proper PCB with ADC an uC placed closely there will be no such delay and the received data will be shifted for one bit? In that case what would be a benefit of using flip flop and not just shift the received data by one bit in the software on uC? Am I missing something here?

Best regards,

Rok

  • 0
    TI__Guru**** 182371 points
    Hi Rok,

    Where are you measuring the ADS8353 signals on your o'scope? Are you monitoring at the controller side or at the ADC side of those 10cm wires? The breadboard and wires can have an impact of the signal integrity. The potential issue that I see is you could miss the MSB, so a simple 'shift in software' may not work out for you.
  • 0
    TI__Guru 67346 points
    Hello Rok,

    I agree that it's possible to read and write to the ADS8353 without issue in some cases. However, given the discrepancy between your scope and uC, I would guess that you are correct in saying that timing delays or logic thresholds might be just good enough to work in your current design. I think the benefit of using the D flip-flop vs. shifting the data in software is that you are assured to capture the data correctly and not miss the MSB. As you found, the SPI definition in the ADS8353 does not follow a conventional SPI mode, so the flip-flop is a more reliable solution for using a standard uC SPI peripheral.

    Regards,
  • 0 in reply to Ryan Andrews
    Prodigy 50 points
    Dear Ryan and Tom.

    Thanks for prompt reply. It doesn't matter where I probe the SDO line (at the converter side or directly at uC pin) I always get expected results (as per the datasheet), so not a conventional SPI mode. But uC somehow reads the correct values as it would be a conventional SPI. I got my custom PCBs delivered and will try it also on them as soon as I will have time.

    But to be honest I don't get why I would miss MSB. In any case for ADS8353 must be pre-cloced with 16 pulses before it starts to output conversion data. And due to the nature of the SPI I anyway capture also "empty" bits. So in any case I have all 48bits of data per conversion in my uC. So it is just the matter of shifting for one bit if it turns out that is necessary. As long as capture of the bit stream is alway repeatable, I see no problem.

    The main reason why I am not in favor of using additional components in my application is that I am running out of the space on my PCB for one sided load. If I am to put additional components on it I must use two sided load, which I am trying to avoid...

    Best regards,Rok

    p.s. For anybody possibly interested. I managed to use ADS8353 dual SDO mode with STM32F4 by utilizing two SPI peripherals. One acts as a master (MISO connected to SDA A of ADS) and one as a slave with MOSI connected to SDO B of ADS. The master SPI provides clock for both the ADS and the slave SPI peripheral and data of both SPIs' data registers are fetched by two different DMA streams to two individual buffers. In that way, the overhead is minimized and also data from both channels is nicely structured for further processing.
  • 0 in reply to Rok Kimovec
    TI__Guru**** 182371 points
    Hi Rok,

    If you are getting good data, that's really all that maters. I had forgotten that you need to have additional clocks ahead of the MSB output, so in this case you won't be missing anything. Do let us know how the production boards work out for you and thanks for the tidbit on the dual output mode operation!