First rule of thumb when driving ADC inputs


Engineers like to simplify the design process using many rules of thumb. One of my favorites is to always drive the inputs of an analog-to-digital converter (ADC) with a low impedance source. Why do I like this one so much? Because it offers many benefits for a precision data acquisition block.

Let’s start by reviewing a common application in which a high-voltage signal source needs to be level translated to the required ADC input range. The simple voltage divider in Figure 1 could solve this problem of level translating a +/-5V signal to a 0-5V. The equivalent impedance Req of the voltage divider is the parallel combination of R1 and R2.

So how does this finite source impedance affect your data acquisition system?

Figure 1

High source impedance introduces both linear and non-linear errors during the data acquisition. Some of the major errors resulting in poor SNR and THD of the data acquisition are:

  • Gain error: Source impedance at the input of the ADC forms a voltage divider with the input impedance of the ADC. This input voltage drop across the source impedance introduces a gain error in the measurement. Keeping the source impedance low will help keep this systemic error small.
  • Settling time error: To make a precise conversion, the ADC inputs need to be settled within the available acquisition time of the data converter. The sampling capacitor inside the ADC is only allowed to charge during this acquisition time. The source impedance at the inputs of the ADC, along with the input capacitor of the ADC, creates additional time constants. Thus, this low-pass filter would introduce errors in the sampled signal due to settling errors.
  • Distortion: The low-pass filter I mentioned above that’s created by the source impedance and the input capacitance also introduces a signal-dependent distortion during the conversion. The distortion results from the inherent non-linearity in capacitors, which depends on the voltage stored across them. The input current used to sample the input signal creates an error voltage across the source impedance. For a sine wave input signal, this error contains harmonics, and degrades the distortion of the system.

The impact of source impedance can be significant when driving the ADC inputs in a precision data acquisition system. Hopefully my rule of thumb helps – always drive the inputs of an ADC with a low impedance source.

To get some more recommendations on how to drive ADC inputs, you might want to check out this TI Precision Design, which provides techniques for extracting the highest performance from your ADC: Data Acquisition Optimized for Lowest Distortion, Lowest Noise, 18bit, 1MSPS Reference Design.

Now that I’ve shared my favorite rule of thumb, what are some of yours when driving an ADC? I hope you’ll tell us below. 

  • Putting a op-am having high curent output-,low output resistance and high impedance input as a buffer between high resistance source  and ADC will be good choice?

  • Hi Vaibhav,

    Your reference design article "Data Acquisition Optimized for Lowest Distortion, Lowest Noise, 18bit, 1MSPS Reference Design" is excellent. You cover a lot a ground and mention issues that are normally not covered, like the distortion trade-offs when choosing between using an inverting vs noninverting op amp configuration. There is a good discussion about this by Samuel Groner at www.sg-acoustics.ch/.../ic_opamps  He discussses this and then supplies test data on LOTS of opamps.  I like the way you explain SNR, SINAD, and THD and the relationships between them. Also, op amp nonlinearity is usually not discussed and you cover that along with noise analysis. Plus you give all the relevant design equations.

    The section on buffering the reference is also very throuogh. I learned the hard way about making sure the op amps were stable into filter capacitor loads and I like the choice of using a composite amplifier for the buffer, a technique you don't see much anymore.

    I do have a question. I don't understand Figure 22.  Do the green lines just indicate the change in the reference voltage? When I subtract the voltage values on the left vertical scale I get 2.1 uV.

    To drive ADCs, I have used the dual feedback method coverd by Tim Green in part 10 of his 15 part article on Op Amp stability. The dual feedback approach can work well, but the circuit has to be carefully evaluated.

    Mark F

  • What about negative impedance, say from an instrumentation amplifier with a series ferrite bead and R/C values at the AINx pin? How does negative impedance, one or more megohm effect acquisition timing? Does the lower or negative source impedance actually improve transient isolation and settling/acquisition times? There must be some kind of trade off involved?

  • Hi BP101,

    In general,  the SAR ADCs is driven with an RC charge kickback filter and a low impedance source such as a relatively high bandwidth amplifier. The capacitor in the RC charge kickback filter works as a large charge bucket providing instantaneous charge to help replenish the internal ADC sample-and-hold capacitor.  The large capacitive load may cause amplifier stability issues, therefore the resistor in the RC filter helps by isolating the amplifier from the capacitive load and improving stability. The complete circuit, amplifier and RC kickback filter, and the ADC internal sample-and-hold needs to completely settle within the Least Significant Bit (LSB) resolution of the ADC during the acquisition period.  

    Most instrumentation amplifiers are relatively low bandwidth, and their output impedance over frequency may be high.  Therefore, in many cases, instrumentation amplifiers may only be able to drive SAR ADCs at relative slow sampling rates in to a few  10s to 100s kSPS range.  The RC filter components in front of the instrumentation amplifier must be carefully selected for both stability and settling.  

    In cases where high sampling rates are required, instrumentation amplifiers are typically buffered with a higher bandwidth amplifier to recharge the ADC’s sample-and-hold and settle within the shorter acquisition time.  Since the amplifier needs to replenish the charge and settle to the target voltage; I don't believe the bead will improve settling.

    Below is a link for an application note of a instrumentation amplifier driving a SAR ADC at 200kSPS (without buffer); and a second application note showing the same instrumentation amplifier buffered, driving the SAR ADC at full data rate of 1-MSPS.  

    www.ti.com/.../sbaa245.pdf

    www.ti.com/.../sbaa277.pdf

    These application notes are part of the "Analog Engineers Circuit Cookbook: ADCs" collection.  These are sub-circuit ideas that include design step-by-step instructions.  All circuits are verified with SPICE simulations.

    Analog Engineer's Circuit Cookbook: ADCs:

    www.ti.com/.../slyy138.pdf

    Thank you,

    Kind Regards,

    Luis C.

  • Hi Luis,

    Thanks for your extensive feedback. However negative impedance being well below  DC impedance measures is what I was referring to.  Spice models AC analysis impedance differs greatly from DC impedance measures of the same RC input filter. Since then reading other sources suggest Cext being fairly large reduces input  impedance but text did not specify linear (DC) or periodic (AC) impedance as to how it effects Rs impedance of SAR input structures and sample acquisition groups.

    As to the instrumentation amplifier such as INA282 typical 10Khz bandwidth, SAR @1MSPS struggled to make any sense of the output even with simple RC filter. The INA240  even with 400kHz BW roughly 100kHz BW @10kHz was not much better even with very low input impedance. Yet SAR 2MSPS versus 1MSPS made a big improvement to group acquisition with a fairly modest RC filter Rs 550 ohms AC impedance @12.5kHz. Source SPNA118B–September 2011 ADC Source Impedance for Hercules™ ARM® Safety MCUs.