Monitoring the voltage level of a coin cell in a portable device or in back-up service is a common, simple application for modern CMOS operation amplifiers (op amps).

Figure 1 shows an implementation using the 1.8-V, OPA333 zero-drift op amp. The coin cell has a voltage of 3 V, while the circuit is powered by a 3- to 5-V level.

Oddly, I’ve had customers report that the circuit drains the coin cell long before the expected life; in just a matter of days, or even hours! These customers found when the op amp was removed, the coin cell remained charged. That piqued my curiosity, and I began an investigation to find out what was happening.

  

Figure 1 - OPA333 unity-gain amplifier connected to monitor coin cell voltage

A popular coin cell, the lithium CR2032, is rated at 175 mAh capacity and 200 uA continuous current. The OPA333 input bias current is typically 70 pA. That alone wouldn’t deplete the cell for years. Something else was draining the battery.  A close look at the OPA333 internal schematic revealed a plausible discharge scenario.

Figure 2 shows a block diagram of the amplifier core and its input ESD protection. Remember that most ICs are protected against ESD during out-of-circuit handling. The ESD cells are designed to be off under normal operating conditions.

The OPA333 ESD input protection has low-leakage steering diodes connected from each input, to the supply lines. An ESD clamp connects between those lines. These diodes are normally reversed biased. However, if the supply voltage V+ is turned off, becoming high impedance, diode D3 can become forward biased. Then, the amplifier core and anything else connected to V+ can drain current from the coin cell.

The OPA333 quiescent current is only 17 uA, so it is probable other components connected to the +V supply line were drawing current too.

Figure 2 - Internal block diagram shows current path through D3 from the non-inverting input to +V supply line

Some op amps have a shut-down pin. When in that mode, they draw a tiny amount of supply current. However, if the ESD cell uses the Figure 2 design, the diode can still conduct current.

The solution is to employ an op amp with a different ESD cell design.

Figure 3 shows the ESD cell design used in the TLV2450 rail-to-rail input/output op amp. It uses a fast, low-leakage clamp - similar to a zener diode. It turns on fast and limits applied voltages to a safe level during an ESD event. There is no internal current path to the VDD pin.

Figure 3 - The TLV2450 uses an input ESD clamp. There is no internal current path from the input to the VDD pin.

It may be difficult for an engineer to determine the ESD cell design an amplifier uses. One hint can be found in the amplifier’s data sheet. When you look at the Absolute Maximum Ratings, if the signal input has a range listed, such as -0.3 V to (V+) + 0.3 V, the 0.3 V is a limit that assures the ESD diodes remain off. Any higher, and they may turn on.

If in doubt, visit our Precision Amplifiers Forum here in the E2E™ Community and submit a question. One of our Applications Engineers will research it for you.

Anonymous
  • Hello Thomas,
    thanks for the reference to the OPA192 datasheet; figure 65 is indeed very nice and would answer almost all questions relating to ESD and EOS that most users would have.  It would be great if this type of diagram could be included with all product datasheets - it would certainly reduce the confusion out there. When a prototype is not behaving as expected, one of the fault-finding items on my checklist is: is some ESD-EOS protection circuit being triggered?  That question is much easier to answer if a figure such as 65 exists.  There is one line in Section 8.3.7 that, IMHO, is key: "This protection circuitry is intended to remain inactive during normal circuit operation." (my italics).

    Just a quick comment on that datasheet: I noticed that section 8.3.1 shows how the OPA192 does not have the back-to-back diodes across the inputs, which is an anti-ESD-EOS measure present in many other opamps.  Section 8.3.7 and in particular Figure 65 is located quite a few pages away from this section, and there seems to be no cross-reference between the two - so the casual reader looking for info on ESD-EOS may miss one or the other.  It may be worth considering moving these two sections to be adjacent to each other, or perhaps even combined into one section.  Since 8.3.1 only discusses the input pins, perhaps one may consider it to be a sub-section of 8.3.7. 

    Thanks again, cheers.

  • Hello Fabio,

    That is a good suggestion and the idea had occurred to us some time ago that we needed to provide that level of information to our product customers. We now include a top-level schematic in many of our Precision Amplifier datasheets showing the internal ESD cells. For example, have a look at the OPA192 datasheet, Section 8.3.7, "Electrical Overstress." The datasheet section nicely depicts the internal ESD cells and their internal connections. I do think we need to carry this idea through to each and every one of our new products so that the information is readily available when needed.

    Thanks for your feedback and suggestion!  - Regards, Thomas

  • Thanks for the post Thomas, this is very helpful.  I agree that the datasheets make it difficult to determine which type of ESD a part has.  Perhaps a simple addition to the datasheet would provide clarity on this matter: include a row in a table that lists the pins internally connected to the Vcc pin by any part of the chip.  In the case of ESD type 1 (clamp diodes to GND and VCC), the list of these pins will include the input pins, whereas for ESD type 2 (Zeners to GND) the input pins will not be included.  
    Of course, a better solution would be a simple schematic diagram showing the ESD protection - not in all its details of course, but sufficient for the purpose of establishing which pins could supply current to the Vcc pin.

  • Hi Sean,

    The TLV341 is produced by another group within TI, and I unfortunately don't have its internal schematic. Therefore, I can't be sure what input ESD cell design it uses. That said, I don't think the maximum differential input voltage specification (+/-5.5 V max) provides the information needed to determine if there are ESD diodes connected from the inputs to the supply rails. Usually, the maximum input voltage range has the clue I mentioned in the blog, such as -0.3 V to (V+) + 0.3 V where any further increase in the voltage begins to turn on the ESD diode.

    I've contacted an Applications Engineer in the group that produces the TLV341 requesting the ESD cell information. I'll post any information that I receive.

    Regards, Thomas

  • Hi Thomas,

    I was looking at the datasheet here - www.ti.com/.../tlv341.pdf.  The absolute maximum differential input voltage listed on page 4 is +/- 5.5V.  This seems to indicate that there are not TVS clamps from the inputs to the Vdd rail which would have a max input rating more like (V-) -0.5V to (V+) +0.5V.

    Thanks, Sean