The mystery of the depleted coin cell

Monitoring the voltage level of a coin cell in a portable device or in back-up service is a common, simple application for modern CMOS operation amplifiers (op amps).

Figure 1 shows an implementation using the 1.8-V, OPA333 zero-drift op amp. The coin cell has a voltage of 3 V, while the circuit is powered by a 3- to 5-V level.

Oddly, I’ve had customers report that the circuit drains the coin cell long before the expected life; in just a matter of days, or even hours! These customers found when the op amp was removed, the coin cell remained charged. That piqued my curiosity, and I began an investigation to find out what was happening.


Figure 1 - OPA333 unity-gain amplifier connected to monitor coin cell voltage

A popular coin cell, the lithium CR2032, is rated at 175 mAh capacity and 200 uA continuous current. The OPA333 input bias current is typically 70 pA. That alone wouldn’t deplete the cell for years. Something else was draining the battery.  A close look at the OPA333 internal schematic revealed a plausible discharge scenario.

Figure 2 shows a block diagram of the amplifier core and its input ESD protection. Remember that most ICs are protected against ESD during out-of-circuit handling. The ESD cells are designed to be off under normal operating conditions.

The OPA333 ESD input protection has low-leakage steering diodes connected from each input, to the supply lines. An ESD clamp connects between those lines. These diodes are normally reversed biased. However, if the supply voltage V+ is turned off, becoming high impedance, diode D3 can become forward biased. Then, the amplifier core and anything else connected to V+ can drain current from the coin cell.

The OPA333 quiescent current is only 17 uA, so it is probable other components connected to the +V supply line were drawing current too.

Figure 2 - Internal block diagram shows current path through D3 from the non-inverting input to +V supply line

Some op amps have a shut-down pin. When in that mode, they draw a tiny amount of supply current. However, if the ESD cell uses the Figure 2 design, the diode can still conduct current.

The solution is to employ an op amp with a different ESD cell design.

Figure 3 shows the ESD cell design used in the TLV2450 rail-to-rail input/output op amp. It uses a fast, low-leakage clamp - similar to a zener diode. It turns on fast and limits applied voltages to a safe level during an ESD event. There is no internal current path to the VDD pin.

Figure 3 - The TLV2450 uses an input ESD clamp. There is no internal current path from the input to the VDD pin.

It may be difficult for an engineer to determine the ESD cell design an amplifier uses. One hint can be found in the amplifier’s data sheet. When you look at the Absolute Maximum Ratings, if the signal input has a range listed, such as -0.3 V to (V+) + 0.3 V, the 0.3 V is a limit that assures the ESD diodes remain off. Any higher, and they may turn on.

If in doubt, visit our Precision Amplifiers Forum here in the E2E™ Community and submit a question. One of our Applications Engineers will research it for you.

  • Nice blog. Do you mean than in TLV2450, ESD prtection is not available for input voltage greater than VDD ?

  • Hi Deepak,

    The ESD protection is in place and effective against out-of-circuit ESD events. Those voltage levels far exceed the normal in-circuit VDD levels. The ESD cells should remain completely off under normal operating conditions when VDD is present.


  • Good experience Thank you.

  • Ahmet,

    You are welcome.

    Regards, Thomas

  • Without even knowing what the insides of the op-amp look like I could have predicted this would happen.

    Many years ago as a student, I had a similar situation with logic devices and older JFET op-amps. In those cases it was simple to deduce there was leakage into VCC.

    In this case it is as clear as day its the ESD diodes. This also happens with A/D converter inputs on microcontrollers where a battery is monitored. What I usually do is ensure the measurement path has the highest possible impedance to ensure the battery doesn't get drained at all.

  • Hello Jason,

    Thanks for reading and your comments.

    Yes indeed cell discharge can occur with other analog ICs if they use the same kind of input ESD cell circuitry. We have had reports of very low power A/D converters draining a cell through their input and found the same cause at work.

    Regards, Thomas

  • Sometimes while designing complex systems overlook minor details!! :P

    In overconfidence sometime we overlook minor data in datasheet and that the biggest pitfall!

  • Hi Suyog,

    I think that the engineers that create the data sheets try to be as thorough as possible, but they can overlook unique electrical conditions encountered in some circuit designs. As we learn of those conditions we do try to include information to help them avoid potential circuit pitfalls. I know we are making extra efforts to make our data sheets as complete as possible to help the designer be successful.

    Thanks for reading and commenting!


  • Could TLV341 be used in place of TLV2450 and still avoid battery drain?  It appears to have the same ESD protection scheme based on the final note about signal input in Absolute Maximum Ratings.

  • Hi Sean,

    Can you quote, or indicate, the specific note in the TLV341 data sheet you are referencing? I looked over the Absolute Maximum Ratings... and the notes, but I am not sure which one you are referring to.

    Thank you, Thomas

  • Hi Thomas,

    I was looking at the datasheet here -  The absolute maximum differential input voltage listed on page 4 is +/- 5.5V.  This seems to indicate that there are not TVS clamps from the inputs to the Vdd rail which would have a max input rating more like (V-) -0.5V to (V+) +0.5V.

    Thanks, Sean

  • Hi Sean,

    The TLV341 is produced by another group within TI, and I unfortunately don't have its internal schematic. Therefore, I can't be sure what input ESD cell design it uses. That said, I don't think the maximum differential input voltage specification (+/-5.5 V max) provides the information needed to determine if there are ESD diodes connected from the inputs to the supply rails. Usually, the maximum input voltage range has the clue I mentioned in the blog, such as -0.3 V to (V+) + 0.3 V where any further increase in the voltage begins to turn on the ESD diode.

    I've contacted an Applications Engineer in the group that produces the TLV341 requesting the ESD cell information. I'll post any information that I receive.

    Regards, Thomas