RE: How to layout a PCB for an instrumentation amplifier

Kuba Sunderland-Ober — Fri, 06 Oct 2023 00:26:40 GMT

The resistance contribution from the traces between input series resistors and the shunt resistor is dwarfed by the mismatch between R1 and R2 just due to their tolerance. So, DC offset introduced by the input bias is solely due to R1-R2 imbalance. DC CMRR won’t be affected much.

however, AC CMRR suffers from any asymmetries on in amp inputs. The layout must be symmetrical from the input pins to the signal source. Parasitic capacitances to the ground plane must be balanced between inputs.

If symmetric layout is not possible due to space constraints, the non-symmetric layout has to be optimized by EM modeling and then careful measurements to ensure that parasitics from both inputs to adjacent copper fill are balanced. If EM modeling is not available, a test PCB has to be made with asymmetries stepped by say 1 mil of spacing, over several mils. That way the most balanced layout can be chosen by measurement only. Physical models beat numerical models every time as long as they are affordable. In this case, a small test PCB costs next to nothing.