Measuring additive jitter in fanout buffers


If you’re working in the communications industry, then you are probably familiar with the effects of jitter on the performance of your system.  Jitter will degrade the performance of data converters and introduce bit errors in high-speed digital systems. It seems intuitive that adding noise to a clock will result in an increase in noise somewhere else in the system.  I always try to minimize the total jitter by selecting components that contribute the least amount of additive jitter. Additive jitter, as its name implies, is the noise added by components between the clock source (such as a synthesizer or oscillator) and the devices being clocked. This additional noise increases the uncertainty of the clock resulting in an increase in jitter.

In practical systems, a clock source will need to drive several devices, so clock buffers (commonly known as fanout buffers) are used to duplicate the signal source and provide higher drive levels. 


Figure 1. A fanout buffer is used to create many copies of a single input frequency.

A good example of this is the LMK00304 fanout buffer.  Clock buffers contribute additive jitter, which mostly affects the wideband noise of the clock.  It can be calculated by using a root-sum-squared calculation as shown in figure 2.

Figure 2. The cascading of clock fanout buffers contributes additive jitter to the driven devices

The additive jitter can be measured by using a signal source (J1) to measure the total integrated jitter and then adding the buffer and taking the same measurement at the output.  But be careful… if you use a traditional signal generator, the noise level of the clock may mislead you to think the contributed additive noise is insignificant.

A good measurement technique is to ensure that the signal source used for the measurement is far less noisy than the device being measured. For example, using a test setup consisting of an Agilent E5052 signal source analyzer and a Wenzel 100 MHz oscillator (with signal conditioning) we’ll measure roughly 46 fs of integrated jitter.  Placing a buffer after the clock and taking the same measurement results in a total integrated jitter of roughly 102 fs.  To calculate the additive jitter, use the following equation:

Our test setup results in an additive jitter of roughly 91 fs.  If we change our clock source to something likely to be on your bench such as a high quality signal generator, the source jitter will rise to roughly 150 fs.  Here’s where it gets interesting… and less intuitive.  If we now place the same buffer after this noisy source and again measure the total integrated jitter, it will roughly be the same leading us to believe the additive jitter is negligible.

So if you’re comparing data sheets of various vendors’ clock buffers, make sure to take a look at the parameter notes (or make a call to the applications engineer) to see how the jitter measurements were made.  The jitter numbers might be misleading if the noise of the clock source was high relative to the device being measured.  Keep this in mind while making your own measurements as well… or you may find yourself looking for additive jitter in all the wrong places!  Till next time…

Want more?

Watch the Engineer It video to see how to measure additive jitter in a fanout buffer. To learn more about TI’s fanout buffer products, click here. For technical support with your next design, go to the Clocks & Timers Forum in in the TI E2ETM Community, where you can search for solutions, get help, share knowledge and solve problems with fellow engineers and TI experts.  You can read all of my Analog Wire blogs by clicking here.