I’ve been watching the evolution of bus structures since I was a young designer in the early 1980s. From the humble S-100 and AT bus to the blazing speed of PCIe Gen-3, I have seen a few changes, most notably serialization. To go faster, you either needed to speed up the clock and keep every transmission line electrically equal in length (not easy), or serialize the data and embed the clock. This brings me to my topic today – high performance serialized bus standards.
It’s not uncommon to find a variety of different high-speed standards within any number of modern computing platforms and peripherals. These include PCI Express, USB, Thunderbolt, Serialized Advanced Technology Attachment (SATA) and Serialized Attached SCSI (SAS). As mentioned earlier, many of these standards have evolved from parallel bus structures into their current serialized form as a way to overcome timing skew and improve reliability. These standards are also increasing in speed as they evolve, leading designers to work harder to guarantee error free data transmission. I see this challenge all the time!
Signal integrity and standards
With each revision of these standards, certain requirements are established to make sure each channel can sustain full data throughput in all conditions. That is, there are limits placed on the jitter tolerance for the standard. When dealing with earlier serial standards such as PCIe Gen-1 (2.5 Gbps), signal integrity on FR-4 was addressed with careful layout. Each standard revision has traditionally doubled the performance of its predecessor. For instance, PCIe Gen-3 has twice the throughput of PCIe Gen-2, even though the raw data rate is only 8 Gbps (versus 5 Gbps for Gen-2). This was achieved though PCIe Gen-3’s more efficient coding (128b/130b) vs. PCIe Gen-2’s 8b/10b coding.
With each revision’s higher bandwidth, the throughput of these standards are doubling, which is making the job of designing high-speed error free (BER of 10-12 or better) channels much more difficult, especially when trying to control PCB costs and remain on FR-4. Here at Texas Instruments, we’ve been helping customers by providing several technologies to actively improve channel signal integrity – namely equalizers, retimers and drivers. With the trend to go faster, and with so many different standards, the problem is compounding. But we never sleep… so read on!
All in one solutions
To get around the linear loss, crosstalk and other jitter inducing nightmares at 5 Gbps and greater speeds, I often recommend placing active components in the data path to improve the channel signal integrity. Depending on the standard, you have many options. It’s important that you pay close attention to picking the right devices since many of the standards use out-of-band (OOB) signaling. If you select the wrong repeater, you could accidentally block these signals and kill the link. To solve this problem, TI has announced a family of multi-standard/multi-protocol repeaters starting with the DS125BR800A. It’s an 8-channel, unidirectional 12.5 Gbps repeater that supports PCIe Gen-1, Gen-2, Gen-3, and SATA 1.5-Gbps, 3-Gbps and 6-Gbps interface standards, as well as all the SATA standards to 6 Gbps (Gen-2).
So the next time you’re thinking about implementing any of these high-speed bus standards, check out our portfolio of signal conditioner devices and remember that going fast just got a lot easier! Till next time…
Oh, in case you’d like to read more on how to deal with channel loss and other OOB and rate adaption challenges, check out this article I wrote on Multi-Protocol ICs Drive Data Networks.
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