How low is low power?


Are all of you familiar with the term micro power? For linear devices, this usually means a quiescent current of 50uA or less. More recently the term micro gave way to the term nano power, which usually refers to a sub 1uA quiescent.

There are some pretty obvious tradeoffs to make and some not so obvious challenges at the design stage. With very little biasing current, the designer must choose whether to use most of it in the input stage to get a decent noise floor or divert it to the output stage. Why? It is because when you ask for a very low power device, you’re likely to get a horrendous noise floor. 

At this point, you have two options:

  1. Live with it
  2. Filter the heck out of it

But wait, if you use an active filter doesn’t that entail more power consumption?  And another thing, if there’s very little current for the output stage then how do we know our device will sustain a 20pF cap load from the probe? You think it’s funny? Well, I’ve witnessed it myself years ago on first silicon which needed several iterations.

There’s also another point to consider, which is that of speed limitation.

Since the device is starved from current, don’t expect much in terms of slew rate and bandwidth. Of course, depending on the process that is chosen the  results will vary. Bipolar devices have a higher transonductance (gm) which ultimately determines the bandwidth (BW=gm/2πCc).

To get an idea of how low is low power, take a look at the new TLV3691 which consumes only 150nA. That's 135nW at sub 1V operation current.