JESD204B: Understanding subclasses (part 1)


In this blog, I’ll look at a key feature of the JESD204B standard that defines a method to achieve deterministic latency for each link and subsequently multi-device synchronization. 

Some applications, such as synchronous sampling, multi-channel phase arrays and gain control loops, are sensitive to latency, but the legacy JESD204 and JESD204A data converter interface standards do not provide a defined means to achieve deterministic latency. They rely instead on very strict layout and timing requirements. Thankfully the newer JESD204B standard provides more flexibility. It addresses deterministic latency in three subclasses: subclass 0, subclass 1 and subclass 2.

JESD204B subclass 0

Subclass 0 does not provide support for achieving deterministic latency, but it does enable backwards compatibility to JESD204A while still allowing usage of the higher 12.5Gbps lane rates of JESD204B (JESD204A lane rates were at 3.125Gbps). It also supports alignment of multiple lanes and multiple devices; however, special considerations are required for multiple analog-to-digital converters (ADCs) and digital-to-analog converters (DACs).

When using subclass 0 with multiple ADCs, the RX logic device (FPGA) combines the SYNC signal for each device.  It then distributes the SYNC signal so that all ADCs see the falling edge of SYNC in the same frame clock period. The ADC device clock edge that samples the assertion of the SYNC signal is also used to reset and align internal clocks within the different ADC devices. The ADC device clocks must be phase aligned to achieve synchronization across multiple devices. This requires very tight control on the SYNC, frame and device clocks for each of the ADC devices. 

When using multiple DACs in subclass 0, you’ll need a separate inter-device RX clock synchronization interface to align the internal clocks of the DAC. This ensures time alignment of the RX blocks in each DAC. The TX logic block (FPGA) must combine all of the SYNC signals from each DAC so that the start of ILAS generation at the TX logic block (FPGA) is synchronized across all lanes for the multiple devices.  Figure 1 below shows the critical timing signals required for subclass 0.

Figure 1: Subclass 0 timing signals

Subclass 0 is fully backwards compatible with JESD204A. However, there are some differences in how the timing of the SYNC signal is used for error reporting.  To overcome this, your JESD204B device should allow you to program its error reporting and detection to meet your JESD204A device requirements.

JESD204B subclass 1

Subclass 1 uses an external SYSREF signal as a common reference for multiple devices. SYSREF is source synchronous to the device clock and should come from the same clock source. It can be a one-shot pulse, gapped periodic or periodic signal. In the case of a gapped or periodic signal, the SYSREF must be an integer multiple of the local multi-frame clock (LMFC) to prevent SYSREF from occurring in the middle of a multi-frame.

You can achieve deterministic latency between a TX and RX device when the internal LMFC clocks are aligned to the edge of the device clock when the SYSREF is sampled high. This should also align/reset all the internal clocks of the TX and RX devices. Furthermore, you can achieve multiple device synchronization by ensuring that the deterministic latency is the same for each TX-to-RX link in your group of devices.

The clock chip will generate the SYSREF signal that meets the setup and hold times of the device clock and must be distributed to each group of TX and RX devices with matched trace lengths to ensure proper alignment of the signals.  You should use a clock chip capable of generating both the SYSREF and the device clocks to minimize the skew between the signals.  The timing signals required for subclass 1 are shown below in Figure 2.

Figure 2: Subclass 1 timing signals with trace length matched SYSREF and device clock groups

It is not mandatory for the clock chip to generate the exact same SYSREF for all TX and RX devices, but the clock chip should generate different SYSREFs in such a way that there is a deterministic relationship between when SYSREF is sampled high in all of the devices. In this case, the latency is deterministic but not minimized. 

Figure 3: Multiple devices using different SYSREF and device clocks with a deterministic relationship

Once you achieve LMFC alignment, you can use future SYSREF pulses to check the alignment of the local frame and multiframe clocks. Be sure to turn SYSREF off during normal operation, as a periodic SYSREF signal runs at a sub-harmonic of the sampling clock and may create unwanted spurs.

The subclass 1 system only uses the SYNC signal in the code group synchronization (CGS) process and is not a critical timing signal. 

Stay tuned for my next blog which will give an overview of Subclass 2, which only requires using the SYNC signal (SYSREF not required).

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