Timing is Everything: JESD204B subclass 1 clocking timing requirements


Most of the JESD204B standard addresses the data interface between logic devices and converters, so what are the clocking requirements? For JESD204B subclass 1, the clocking requirement is quite simple: use the SYSREF rising edge to mark the device clock rising edge which resets the local multi-frame clock (LMFC) of the JESD204B element. Now let’s discuss how to achieve this requirement.

The datasheet of the logic device or converter will indicate the timing requirements for placement of the SYSREF rising edge with respect to the device clock rising edge. Figure 1 illustrates a typical valid SYSREF window after considering set-up and hold timing requirements. Note, only the rising edge of the SYSREF clock waveform is shown. The SYSREF clock may remain high across multiple device clock edges. Only the rising edge of SYSREF marks the device clock edge which resets the LMFC.

Figure 1: Example of valid SYSREF window: Green arrows 2 through 8 indicate valid SYSREF positions  that cause an LMFC reset on device clock edge located at position 11

It is possible to ensure accurate SYSREF placement by careful routing of SYSREF and device clock traces on the PCB, which factors all skew elements. However, if there is an error in design of the PCB, then re-spinning the PCB may be required to resolve the timing problem since a marginal SYSREF rising edge may result in different device clock edges being used to reset the LMFC from power-up to power-up or across devices. This results in a source of non-deterministic latency, which cannot be eliminated by using the RX Buffer Delay. Depending on the application, this ± integer device clock cycle error of LMFC edge position between JESD204B devices may or may not be acceptable.

One solution to ensure a good placement of SYSREF rising edge with margin is to use a clocking device, such as LMK0482x, which supports delay adjustments of the SYSREF and/or device clock. When using a clocking device with delay adjustments, it is possible to simplify PCB design by relaxing or eliminating trace matching requirements because relative SYSREF and device clock phases may be skewed by programming the clock device. Figure 1 illustrates a delay that’s able to adjust the SYSREF rising edge position in 200 ps steps. Shown are seven SYSREF rising edge positions that meet the set-up and hold time, but position 5 gives the most margin to the edges of the set-up and hold windows and is the preferred placement to use in this application.

By designing a system that allows the placement of at least four edges inside a valid SYSREF window, margin of approximately the step size can be ensured in the design. In high-speed systems it may not be possible achieve small enough delay steps to have four placements of SYSREF in the valid window. Figure 2 illustrates three different cases when only two placements of SYSREF are possible in the valid window: (a) placement in middle of window, (b) one placement on edge of window, so other placement has margin, and (c) both placements have equal margin.

Figure 2: Example of valid sample windows for high-speed clocks: Red arrows show smallest margin to edge of valid SYSREF window for each case

The margin for each case in Figure 2 may be calculated for you own system as shown in Table 1.

Figure 2 Case

Approximate Margin

(a) Best

Valid window / 2

(b) Intermediate

Valid window – Step size

(c) Worst

(Valid window – Step size) / 2

Table 1: Timing margin calculations for two SYSREF placements in valid SYSREF window

In these high-speed cases, some giga-sample data converters, such as ADC12Jxxxx, allow shifting the valid window with a very fine delay step to improve SYSREF margin. Some extra considerations in the SYSREF timing margin is that the non-uniform delay step size and jitter can reduce margin.

Finally, there are no phase noise or jitter specifications for the SYSREF clock in JESD204B. However the SYSREF period peak-to-peak jitter plays a small part in the timing margin for SYSREF.

Thanks for joining me, and be sure to check out other blogs in the Timing is Everything series and the JESD204B series.

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