The future of data converter interfaces


I’m a very direct individual, and when I think of data-conversion technology, I quickly categorize it into buckets:

  • Precision:  Typically less than 1 Msps with a high dynamic range (+20 bits).
  • General purpose:  Anywhere from 1 Msps to 20 Msps with a moderate dynamic range (12-16 bits).
  • High speed:   20 Msps to 1 Gsps with a good dynamic range (8-14 bits).
  • Ultra-high speed:  1 Gsps and above.

For lower-speed precision and general-purpose data converters, serial peripheral interface (SPI), I2C or parallel interfaces are more than enough to handle the data rate. But what happens when you can now integrate four or eight digital-to-analog converters (DACs) or analog-to-digital converters (ADCs) that each require 100+ Msps per channel? The digital information overwhelms the standard interfaces.

The solution for multiple data converters at or above 100 Msps has been to use either parallel double-data-rate (DDR) low-voltage differential signaling (LVDS) or serialized LVDS. At first, serializing the LVDS seems logical, but LVDS is limited in performance. When serializing large numbers of moderately fast data converters or small numbers (one to two) of ultra-high-speed data converters, lane speeds will exceed 3 Gbps – this is pushing the limits of LVDS technology. In addition, serialized LVDS requires a clock line to synchronize each lane, while the transmission lines still require matching to prevent skew and jitter from affecting bit error rate (BER).

The first true solution to the steady progression of ever-faster analog data converters is the JEDEC standard JESD204. In the latest revision, B, the interface has moved from LVDS to current-mode logic (CML), which is designed for speeds in excess of 10 Gbps. Additionally, the clock is now embedded into the stream, allowing independent clock and data recovery per lane. The standard also introduced scrambling and 8b/10b encoding to both minimize electromagnetic interference (EMI) and improve data integrity. This migration greatly reduces the number of interconnects required between the data converter and processor or field-programmable gate array (FPGA).

For example, an ADC12D1600 running in dual-edge-sampling (DES) mode provides a sample rate of 3.2 Gsps, which requires 50 electrically matched LVDS transmission lines, whereas the ADC12J4000 only requires eight CML transmission lines (which do not need to be electrically matched). The skew is adjusted by an elastic buffer inside the receiver’s JESD204B interface. This also benefits the package, which shrinks from a 292-pin ball-grid array (BGA) (ADC12D1600) package to a 68-pin very thin quad flat no-lead (VQFN) package (ADC12J4000) that is only 10 mm x 10 mm. So both performance and density benefit from this interface technology (Table 1).

Table 1: Comparison of two similar gigasample ADCs, one with a parallel LVDS interface and the other with JESD204B

However, there are issues with this interface technology: latency and signal integrity. One benefit of parallel LVDS is that the delay between the time the sample is acquired from the ADC (or presented to the DAC) is extremely short. In the case of a gigasample ADC, it is a matter of converting a thermometer code to either 2’s compliment or binary – a straightforward digital single-clock cycle function and the data is immediately available at the outputs. In the case of the JESD204B, the data is scrambled, 8b/10b encoded and finally serialized, which all then needs to be reversed at the receiver. This adds considerable latency in the transmission of the data, even with lane speeds of 12.5 Gbps.

Then there’s signal integrity. CML lanes running at 12.5 Gbps on FR4 can be challenging. Beyond the forward-loss factor of the board material, there can be impairments such as connectors and vias that will add to the overall jitter budget of the interface. For longer transmission lines, a buffer/equalizer may be required such as the DS125BR800A, which can provide receive equalization as well as increased drive including de-emphasis to improve the BER of up to eight lanes – a major factor considering that there is no forward-error correction in the JESD204B standard.

So what does the future hold? In much the same fashion that data centers require faster interconnects, so will high-density or ultra-high-speed data converters. The current JEDEC standard specifies CML transmission lines that can run up to 12.5 Gbps. The next-level standard will take that to 16 Gbps or beyond – possibly 25 Gbps – driving the need for careful signal-integrity management and possibly the introduction of more exotic board materials such as Megtron 7. It is the price of going faster, but the benefits of high-speed serialization coupled with standardized protocols outweigh the issues. Till next time …

JESD204B resources: