In a high-speed printed circuit board (PCB), a via is notorious for degrading signal-integrity performance. However, using via structures is unavoidable. In a typical board, components are placed on the top, while differential pairs are routed in inner layers where they lower electromagnetic radiation and pair-to-pair crosstalk. Vias must be used to connect components on the board’s surface to the inner layers.
Fortunately, it’s possible to design a transparent via that minimizes performance impact. In this post, I’ll discuss the following:
1. Basics of a via structure
Let’s start by examining the elements of a simple via that connects a top trace to an inner trace. Figure 1 is a 3-D diagram showing a via construction. There are four basic elements: the signal via, via stub, via pad and anti-pad.
Vias are metal cylinders that plate through holes between the top and bottom layers of a board. Signal vias connect traces at different layers. Via stubs are the unused part of the via. Via pads are donut-shaped pads that connect the vias to the top or the inner traces. Anti-pads are the circular clearances in each power or ground layer that prevent electrical short to the plane.
Figure 1: 3-D diagram of a single via
2. Electrical properties of via elements
Let’s walk down the signal path to visualize the electrical property of each via element, shown in Table 1.
Table 1: Electrical properties of the via elements shown in Figure 1
A simple via is a series of π-networks made of capacitance-inductance-capacitance (C-L-C) elements formed within two adjacent layers. Table 2 shows the effect of the via dimensions.
Table 2: Intuitive effect of via dimensions
By balancing the amount of inductance and parasitic capacitance, it’s possible to construct a via with the same characteristic impedance as the trace, thus becoming transparent. There’s no simple equation that translates via dimensions into the C and L elements. A 3-D electromagnetic (EM) field solver can predict the impedance of a structure based on the dimensions used in a PCB layout. By repeatedly adjusting the structure’s dimensions and running 3-D simulations, it’s possible to optimize the via dimension to achieve the desired impedance and bandwidth requirements.
3. Building a transparent differential via
As discussed in my previous post, a differential pair must be implemented with a high degree of symmetry between the A and B wires. The pairs are routed in the same layers, and if there’s a need for a via, it must be implemented in both wires at locations close by. Because the two vias of the differential pair are in close proximity, instead of using two separate anti-pads, an oval anti-pad shared by the two vias reduces parasitic capacitance. A ground via is also placed next to each via so that they provide ground-return paths for the A and B vias.
Figure 2 shows a ground-signal-signal-ground (GSSG) differential via structure example. The distance between the two adjacent vias is called a via pitch. A smaller via pitch introduces more mutual coupling capacitance.
Figure 2: A GSSG differential via with back-drill
Don’t forget that the via stub produces severe degradation to high-speed signal integrity at above 10Gbps. Fortunately, there’s a back-drill PCB manufacturing process that precisely drills through the unused via cylinder. Determined by the manufacturing process tolerance, back-drilling removes the unused via metal and minimizes the via stub to less than 10mils.
A 3-D EM simulator is used to design a differential via with the desired impedance and bandwidth. This is an iterative process that repeatedly adjusts the via dimensions and runs EM simulations until achieving the desired impedance and bandwidth.
4. How to verify performance
The differential via design shown in Figure 2 was built and tested. The test sample consists of a pair of differential traces at the top layer, followed by a differential via to the inner traces, then a second differential via connects to the BGA landing pads at the top layer again. The total length of the signal path is about 1,330mils. I measured its differential impedance with a differential time-domain reflectometer (TDR), its bandwidth by using a network analyzer, and its effect on the signal by measuring the data-eye opening with a high-speed oscilloscope. Figures 3, 4 and 5 show the impedance, bandwidth and eye diagrams, respectively. The left-side plots are the test results with back-drilling, while the right-side plots are those without back-drilling. From the bandwidth plot in Figure 5, it’s clear that back-drilling is necessary to achieve high performance at data greater than 10Gbps.
With back-drill, ZDIFF is about 85Ω Without back-drill, ZDIFF is about 58Ω
Figure 3: TDR impedance plots
Insertion loss at 12.5GHz is about 3dB Insertion loss at 12.5GHz is more than 8dB
Figure 4: Frequency responses
With back-drill, data eye is open Without back-drill, data eye is closed
Figure 5: Data-eye diagrams at 25Gbps
TI has a rich portfolio of high-speed signal-conditioning integrated circuits (ICs) such as retimers and redrivers. They help mitigate imperfections and high insertion loss from all types of differential pairs, enabling reliable data communication and extending transmission distance for modern systems.
Leave a note below – I’d love to hear your feedback on this post or anything you’d like to learn in future “differential pairs” posts.
Thanks for posting this, very cool. Are there any changes that can be made to improve the non-backdrilled case, such as increasing the via pitch? Is the stub capacitance in this structure independent of the via pitch?
This also raises the point that if back drilling is not feasible, then the signal layers in the PCB stack up should be chosen carefully to reduce the size of the stub. For example, signals from the top layer should traverse to the inner signal layer closest to the bottom.
Hi Matt,Thanks for reading this blog and provided your feedback.
In cases where back-drill is not an option, then the choice is to carefully choose the stackup for minimizing the length of the stub. To achieve this goal, the signal layer should be moved towards the bottom side of the board, so the un-used via stub is shortest; or use the entire length of the via from top-to-bottom layer, so the via stub is zero.
In cases where stub length do exist but short, they present a small capacitive effect. Like your suggestion, it is still possible to raise the impedance of the via by changing the via structure's dimensions (eg increase anti-pad size, reduce via diameter, increase via pitch etc). This increase in impedance will effectively add some inductance to counter-act the stub capacitance.
I'm a student and I have a 4 layers PCB with dielectric constant 4.2.
the board thickness is 63mils (1.6mm).
the stack-up is as follow:
I have implemented some LVDS vias from L1 to L4.
could you please give me a suitable via size to have 100 Ohm impedance?
it's my email: email@example.com
All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.
TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs andembedded processors, along with software, tools and the industry’s largest sales/support staff.