What you need to know about internal ESD protection on integrated circuits


Most of the integrated circuits that I work with are electrostatic discharge (ESD)-sensitive. In spite of all the care we engineers take, it is nearly impossible to eliminate static electricity completely. Semiconductor manufacturers add chip protection to make their devices more resistant to stray electric fields and currents, but their data sheets do not explicitly state the exact nature of the protection measures. So in this post, I will cover some of the more common methods used for ESD protection and what sort of constraints these methods put on the circuit. I will use a fully differential amplifier (FDA) as an example. Operational amplifiers will use the same ESD structures, but they would have only one output pin.

For most semiconductor devices, the power-supply voltages represent the maximum and minimum voltage potentials present on the chip. Even when that is not the case, it is still normal to use the power supplies as the primary means to move harmful currents or potentials from the device. Every device has an absolute maximum supply voltage that it can tolerate before becoming damaged. In an ESD event, it is important that the power-supply voltages do not become too large. In addition to the on chip ESD protection circuits system designs also have capacitors that provide power-supply bypassing. These capacitors can provide a lot of benefit during an ESD event by absorbing transient voltage spikes. But they are only helpful after the chip is soldered to the board, so there still must be some on-chip ESD protection between the power-supply pins.

The most common form of ESD protection used between the supply pins is a voltage clamp. There are two primary methods used to activate these clamps. The first is a voltage-based threshold, where any voltage over a predetermined voltage threshold will trigger the clamp. It is important to note that these clamps are typically set to a voltage much higher than the specified absolute maximum power-supply voltage. Therefore, an overvoltage condition on the device power supply can damage the device before the ESD protection engages.

Another style of ESD supply clamp is set to trigger based on the time rate of change (dV/dt) of the supply voltage. A typical ESD event would have a dV/dt of several volts per nanosecond – much higher than at device power up. Again, this kind of clamp will not protect against a static overvoltage condition such as that caused by a power spike or by applying the wrong supply voltage.

 

Figure 1: Typical ESD protection structures on an FDA

For the device shown in Figure 1 the equations which give appropriate operating voltages for the input and output pins are shown below.  

                                  (1)

These equations will help with system design or debugging.

ESD protection for output pins typically consists of diodes connected to the power supplies, as shown in Figure 1. These diodes conduct ESD energy into the power supplies, where it is absorbed either by the clamp or by off-chip bypass capacitors and power-supply regulation. For most system designers, the ESD protection on the device output pins is not an issue because the device typically cannot drive the input or output pins into a state where ESD protection is a problem. When the device is disabled or there is no supply voltage applied, however, it is possible that another system component could force the output pins into a state where the ESD diodes would provide a path for current to flow into the power supplies.

Like the output pins, the input pins are usually protected with diodes connected to the power supplies. In addition, many differential input devices will have additional protection diodes between the pins. One of the primary issues with input pins happens when a device has no power applied to the supply pins (V+ and V-), but there is voltage applied to the input pins. If a positive voltage applied to an input pin is large enough, it can flow through the ESD diode and become a phantom power supply for the device. The device behavior can become quite erratic in this case, since it will most likely only be weakly powered on and for short periods of time. Common symptoms of a weakly enabled amplifier are rectified pulses showing up on the device output pins. One remedy for this situation is to choose a device with a power-down option. In this case the power-supply pins will continue to have the proper voltage applied, so power will not flow from the input pins to the supplies.

Another common issue with input pins also occurs when the device either has no power or is in a disabled state. Notice in Figure 1 that the input pins have a series of stacked diodes connected between them. When in an active state, these pins should have the same voltage, so no current can flow between them. When the device is disabled, the inputs are now floating until the voltage potential exceeds the diode voltage drop (typically 0.5V per diode). In the example circuit, this voltage would be around 1.0V. Issues here can arise if the system circuit tries to apply a differential voltage of more than 1.2V to these pins. This might be the case in a multiplexer circuit, where multiple devices are connected to a single signal source, but only one device is active at a time. In this case, the disabled devices would present a nonlinear load to the signal.

ESD diodes are designed to handle current, but only for a microsecond or less. If the data sheet does not include a specification, how much current can a typical ESD diode handle? A good rule of thumb is to restrict continuous current through an ESD diode to less than 10mA.

Knowing how ESD protection impacts circuit operation can help when designing complex systems. Keep in mind the limitations in Equation 1 when designing complex circuits.

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