Transimpedance amplifiers (TIAs) act as front-end amplifiers for optical sensors such as photodiodes, converting the sensor’s output current to a voltage. TIAs are conceptually simple: a feedback resistor (R_{F}) across an operational amplifier (op amp) converts the current (I) to a voltage (V_{OUT}) using Ohm’s law, V_{OUT} = I × R_{F}. In this series of blog posts, I will show you how to compensate a TIA and optimize its noise performance. For a quantitative analysis of a TIA’s key parameters, such as bandwidth, stability and noise, please see the application note, ““Transimpedance Considerations for High-Speed Amplifiers.”

In a physical circuit, parasitic capacitances interact with the feedback resistor to create unwanted poles and zeros in the amplifier’s loop-gain response. The most common sources of parasitic input and feedback capacitances are the photodiode capacitance (C_{D}), the op amp’s common-mode (C_{CM}) and differential input capacitance (C_{DIFF}), and the circuit-board capacitance (C_{PCB}). The feedback resistor, R_{F} is not ideal and has a parasitic shunt capacitance that may be as large as 0.2pF. In high-speed TIA applications, these parasitic capacitances interact with each other and R_{F} to create a response that is not ideal. In this blog post, I will illustrate how to compensate a TIA.

Figure 1 shows a complete TIA circuit with parasitic-input and feedback-capacitance sources.

**Figure 1: TIA circuit including parasitic capacitances**

Three key factors determine the bandwidth of a TIA:

- Total input capacitance (C
_{TOT}). - Desired transimpedance gain set by R
_{F}. - The op amp’s gain-bandwidth product (GBP): the higher the gain bandwidth, the higher the resulting closed-loop transimpedance bandwidth.

These three factors are interrelated: for a particular op amp, targeting the gain will set the maximum bandwidth; conversely, targeting the bandwidth will set the maximum gain.

**Single-pole amplifier with no parasitics**

The first step of this analysis assumes an op amp with a single pole in the A_{OL} response and the specifications shown in Table 1.

**Table 1: TIA specifications**

An amplifier’s closed-loop stability is related to its phase margin, Φ_{M}, which is determined by the loop-gain response defined as A_{OL} × β, where β is the inverse of the noise gain. Figures 2 and 3 show the TINA-TI™ circuits to determine the op amp’s A_{OL} and noise gain, respectively. Figure 2 configures the device under test (DUT) in an open-loop configuration to derive its A_{OL}. Figure 3 uses an ideal op amp with the desired R_{F}, C_{F} and C_{TOT} around it to extract the noise gain, 1/β. Figure 3 excludes parasitic elements C_{F} and C_{TOT} – for now.

**Figure 2: DUT configuration to determine A _{OL}**

**Figure 3: Ideal amplifier configuration to determine noise gain (1/β)**

Figure 4 shows the simulated magnitude and phase of loop gain, A_{OL} and 1/β. Since 1/β is purely resistive, its response is flat across frequency. The loop gain is A_{OL}(dB) + β(dB) = A_{OL}(dB), since the amplifier is in a unity-gain configuration as shown in Figure 3. The A_{OL} and loop-gain curves thus lie on top of each other, as shown in Figure 4. Since this is a single-pole system, the total phase shift due to the A_{OL} pole at f_{d} is 90°. The resulting Φ_{M} is thus 180°-90° = 90°, and the TIA is unconditionally stable.

**Figure 4: Simulated loop gain, A _{OL} and 1/β for an ideal case**

**Effect of input capacitance (C _{TOT})**

Let’s analyze the effect of capacitance at the amplifier’s inputs on loop-gain response. I’ll assume a total effective input capacitance, C_{TOT}, of 10pF. The combination of C_{TOT} and R_{F} will create a zero in the 1/β curve at a frequency of f* _{z}* = 1/(2πR

_{F}C

_{TOT}) = 100kHz. Figures 5 and 6 show the circuit and resulting frequency response. The A

_{OL}and 1/β curves intersect at 10MHz – the geometric mean of f

*(100kHz) and the GBP (1GHz). A zero in the 1/β curve becomes a pole in the β curve. The resulting loop gain will have a two-pole response, as shown in Figure 6.*

_{z}The zero causes the magnitude of 1/β to increase at 20dB/decade and intersect the A_{OL} curve at a 40dB/decade rate of closure (ROC), resulting in potential instability. The dominant A_{OL} pole at 1kHz results in a 90° phase shift in the loop gain. The zero frequency, f_{z}, at 100kHz adds another 90° phase shift. Its effect is complete by 1MHz. Since the loop-gain crossover occurs at only 10MHz, the total phase shift from f_{d} and f_{z }will be 180°, resulting in Φ_{M }= 0° and indicating that the TIA circuit is unstable.

**Figure 5: Simulation circuit including a 10pF input capacitor**

**Figure 6: Simulated loop gain, A _{OL} and (1/β) when including the effects of input capacitance**

**Effect of feedback capacitance (C _{F})**

To recover the phase loss due to f_{z}, insert a pole, f_{p1},_{ }into the 1/β response by adding capacitor C_{F} in parallel with R_{F}. f_{p1} is located at 1/(2πR_{F}C_{F}). To get a maximally flat, closed-loop Butterworth response (Φ_{M }= 64°), calculate C_{F} using Equation 1:

where f_{-3dB} is the closed-loop bandwidth shown in Equation 2:

The calculated C_{F }= 0.14pF and f_{-3dB} = 10MHz. f_{z} is located at ≈7MHz. The feedback capacitor includes the parasitic capacitances from the printed circuit board and R_{F}. In order to minimize C_{PCB}, remove the ground and power planes beneath the feedback trace between the amplifier’s inverting input and output pin. Using resistors with small form factors, such as 0201 and 0402 reduces parasitic capacitance caused by the feedback components. Figures 7 and 8 show the circuit and resulting frequency response.

**Figure 7: Simulation circuit, including a 0.14pF feedback capacitor**

**Figure 8: Simulated loop gain, A _{OL} and 1/β when including the effects of input and feedback capacitance**

Using Bode-plot theory, Table 2 summarizes the points of inflection in the loop-gain response.

**Table 2: Effect of poles and zeros on the loop-gain magnitude and phase**

The 1/β curve reaches a maximum value of . For a Butterworth response, 1/β intersects A_{OL} near its maximum value at a frequency . f_{d} and f_{z} create a total phase shift of 180°. The phase reclaimed by f_{p1} is , which is very close to the simulated 65°.

When designing a TIA, you must know the photodiode’s capacitance, as this is usually fixed by the application. Given the photodiode capacitance, the next step is to select the correct amplifier for the application.

Choosing the right amplifier requires an understanding of the relationship between an amplifier’s GBP, the desired transimpedance gain and closed-loop bandwidth, and the input and feedback capacitances. You can find an Excel calculator incorporating the equations and theory described in this post here. If you are designing a TIA, be sure to check the calculator out. It will save you a lot of time and manual calculations.

**Additional resources**

- Download the application report, “Transimpedance Considerations for High-Speed Amplifiers,” for a quantitative derivation of Equations 1 and 2 in this post.
- Get online support in the TI E2E™ Community Amplifier forums.
- Browse more than 40 training videos on op-amp topics like noise, bandwidth and stability.
- Learn more about selecting the correct amplifier in the application note, “Transimpedance Amplifiers (TIA): Choosing the Best Amplifier for the Job.”
- Search TI high-speed op amps and find technical resources.

Hi,

Could you explain the following

1) Why the source resistance is not considered while calculating the loop gain or Noise gain

2) Can the differential input capacitance be neglected due to virtual ground behavior as explained in your previous post ?