One of my standard interview questions for new college graduates is to describe the non-ideal aspects of an operational amplifier (op amp). While most candidates start with open-loop gain, offset voltage, bandwidth and noise, only a few mention input bias current. Even experienced circuit designers often have questions about input bias current and its effects. In this post, I’ll answer some of these questions and hopefully clear up some misconceptions.
Q: What is input bias current?
A: The term “input bias current” (I_{B}) in datasheets – for both op amps and fully differential amplifiers (FDAs) – refers to the DC currents flowing into or out of the amplifier’s input pins to create a defined operating point during normal operation, as shown in Figure 1.
Figure 1: Definition of input bias current for a simple PNP input stage
Because a MOSFET requires very little DC gate current to operate, the input bias current of a CMOS amplifier is dominated by leakage from electrostatic discharge (ESD) protection cells and other secondary circuits connected to the inputs. The magnitude of this leakage current is small – on the order of picoamps (pA). Since the inputs of bipolar junction transistor (BJT) amplifiers require base currents for proper bias, however, the BJT input bias current is a lot larger – on the order of microamps (µA). Hence, input bias current is an important issue for BJT amplifiers.
Q: Why do you need BJT-input amplifiers?
A: Since CMOS amplifiers have almost negligible input bias currents, why do you even need BJT amplifiers? The answer is that a BJT has much larger transconductance (g_{m}) compared to a CMOS transistor at the same quiescent current. In addition, matching between BJTs is also a lot better, and so is its flicker (or 1/f noise). All three advantages are crucial for high-speed precision amplifiers; hence, BJT inputs are ubiquitous in high-performance op amps and FDAs.
Q: How do you evaluate the effects of input bias currents?
A: While using amplifiers with significant input bias currents often requires some additional design considerations, you might be surprised to find how little they actually affect system performance. Once you understand the effects of input bias current, you can weigh the benefits of a BJT-input amplifier against these effects.
Let’s investigate the effects of input bias currents using the FDA circuit shown in Figure 2. The THS4551 is the newest addition to TI’s family of precision analog-to-digital converter (ADC) drivers. The THS4551 features not only 150MHz bandwidth on 1.35mA I_{q}, but also ±2µV/°C max V_{OS} drift, as shown in Table 1. The BJT-input architecture enables such performance but creates a notable I_{B}.
Figure 2: THS4551 FDA circuit with 1% resistors
Table 1: Key input-referred DC parameters of the THS4551
Focusing on the mathematically simplest case, let’s first assume that the FDAs are always connected with symmetrical feedback elements, since this leads to minimum signal conversion from the common-mode errors to the differential output.
You can calculate the “output referred” offset voltage V_{OOS} in two steps. First, find the amplifier’s positive and negative summing-junction voltages using Equation 1:
Then, use Equation 2 to calculate V_{OUT} based on the gain from the summing junction to the output, which is the noise gain:
Combining Equations 1 and 2 together, you can calculate V_{OOS} at the output as the difference between these two output voltages with Equation 3:
The output V_{OOS} is simply the difference between the input bias currents on each side, multiplied by their respective feedback-resistor values (R_{F}). The gain resistor (R_{G}) has dropped out of the V_{OOS} equation. Intuitively, this is because a small R_{G}, which would have reduced the impact of I_{B} on the summing-junction voltage, also increases the noise gain from summing junction to output, and the two effects cancel each other.
Let’s use the circuit in Figure 2 and the specs of the THS4551 in Table 1 to calculate the worst-case output V_{OOS} from each contributing factor (input V_{OS}, I_{B} and I_{OS}), listed in Table 2.
Contributing factor
25°C max error
Worst gain to output
Worst-case contribution to output V_{OOS} (µV)
Gained up by
Input V_{OS}
±175µV
3.04V/V
±532
Noise gain
I_{B±}
1.5µA
±20Ω
±30
Feedback resistor mismatch
I_{OS}
±50nA
1.01kΩ
±50.5
Feedback resistor
Table 2: THS4551 output referred offset voltage terms for R_{F}=1kΩ, 1%
Now, let’s look at four cases for different resistor values and tolerances in the circuit. For two values of R_{F} (1kΩ and 5kΩ) and two tolerances (1% and 0.1%), Table 3 shows the results.
Case
RF (kΩ)
RF tolerance (%)
Worse-case output V_{OOS} terms (µV)
V_{OS}
1
2
0.1
±526
±3
±50.1
3
5
±150
±252.5
4
±15
±250.3
Table 3: THS4551 output referred offset voltage terms for different R_{F} choices
Similarly, Figure 4 shows the results for the output-offset drift.
Worse-case output V_{OOS} drift terms (µV/°C)
±6.1
±0.11
±0.283
±6
±0.01
±0.28
±0.55
±1.41
±0.06
±1.4
Table 4: THS4551 output referred offset drift terms for different R_{F} choices
A couple of takeaways:
Q: What about input-current noise?
A: Most of this post is about the impact of I_{B} and I_{OS} on offset voltage and offset-voltage drift. Another important effect of input current is added noise. Luckily, noise is just a time-varying offset, so you can calculate the effect of noise just as you calculated the effect of offset. For example, the output-voltage noise due to the input-current noise is simply
Another issue worth mentioning is internal input-bias cancellation. Various cancellation techniques can usually reduce I_{B} from the level of microamps to nanoamps. The I_{OS} will also be reduced, although not nearly as much. However, these cancellation techniques usually increase input-current noise due to uncorrelated noise from the cancellation current. So if noise limits your system’s performance, input-bias cancellation is likely not the right choice.
Conclusion
Compared to CMOS-input amplifiers, BJT-input op amps and FDAs offer many benefits: higher bandwidth at lower power, lower voltage noise and 1/f noise, and better DC precision. They come with one catch, however: higher input bias currents. With careful design, you can evaluate and mitigate the negative effects of the higher input bias currents.
What is your experience dealing with issues due to input bias current? I have only scratched the surface of I_{B} effects, and haven’t mentioned many secondary issues. What more do you want to know? Log in below and leave a comment.
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