A race against the clock: how to determine the power-up states of clocked devices

Many engineers choose flip-flops, shift registers, or other clocked devices for temporary storage and moving small amounts of data. These clocked devices have one or more clock-input pins, typically designated CLK or CP. A clock edge will determine when a specific function occurs; for example, the data may be clocked to an output, or data may be moved from one pin to another. Device data sheets specify whether this happens on the positive or negative edge, and include a truth table for each part.

Often, these truth tables include up and down arrows indicating the clock status. But what happens in that mysterious state before any clock edge has occurred? Consider the SN74AUP1G80, a five-pin D-type flip-flop. If VCC powers up and there is no valid clock edge, the truth table says that the Ǭ output is equal to Ǭ0.

Not very helpful, is it? Actually, it illustrates a design reality. We don’t know what the output will be before the first valid clock edge. When the device turns on, thresholds on internal transistors in the clocked device can float to indeterminate values, resulting in unpredictable signal levels at Ǭ. Typically, under the same conditions, the part will start up with the same output value, but this can vary across temperature and manufacturing lot to another. Therefore, for these clocked devices, it is imperative to wait until VCC has ramped to an appropriate level and a valid clock edge has passed before reading the output.

If the clock edge on a positive-edge-triggered device rises with VCC, I recommend waiting an extra clock cycle, as the clock threshold changes with VCC and any small amount of noise can cause unwanted clocking.

One clever trick you can use to “beat the clock” is to use devices with clear (CLR) (set all outputs to 0) and preset (PRE) (set all outputs to 1) inputs. Typically, in TI data sheets we designate these pins by some form of PRE, CLR or MR (for master reset). Look at the SN74AUP1G74, for example. The active-low CLR and PRE inputs allow engineers to override the clock! When used, these pins allow you to set the output of the device before CLK, giving you more control over the output bus. 

For more advice on powering clocked devices, review these additional resources: