ESD fundamentals, part 4: ESD capacitance

In the third installment of this series, I explored the importance of the clamping voltage of an electrostatic discharge (ESD) protection diode.

Although the main goal of an ESD diode is to protect a system during an ESD event, it has another equally important purpose to fulfill during normal operation: do absolutely nothing. While “doing nothing” may seem like an easy task, the presence of an ESD diode adds parasitic capacitance to the system. During an ESD event, the diode will break down and steer the damaging current to ground. When the diode is conducting, it can be modeled as an offset voltage V_BR (breakdown voltage) in series with a dynamic resistance (R_DYN). During normal operation, the diode is reverse-biased while data (or power) transmits through the trace. As a result, the diode’s depletion region stores electric charge, effectively becoming a capacitor with capacitance value C_L (Figure 1).

Figure 1: During an ESD event, the ESD diode breaks down at voltage V_BR and has a resistance of R_DYN (left); during normal operation, signals pass to the system and the ESD diode acts as a capacitor with capacitance value C_L (right)

If you don’t properly account for C_L, the diode will degrade the signal integrity of data passing through. For high-speed signals such as USB 3.0, USB 3.1 and High Definition Multimedia Interface (HDMI) 2.0, passing the eye-diagram mask test is required in order to achieve compliance with the interface standard. However, increased trace capacitance will increase signal rise and fall times and “shut” the eye. This could potentially push the entire system out of compliance (Figure 2).

Figure 2: A compliant USB 3.1 Gen 2 eye diagram (top); a noncompliant USB 3.1 Gen 2 eye diagram caused by high capacitance (bottom)

Designers usually have a capacitance budget to ensure that the entire system stays within compliance – there is no blanket maximum ESD capacitance requirement applicable to every design. For example, if the traces of system A are shorter than that of system B, system A will have more leftover capacitance to allocate toward ESD protection. Therefore, the ESD diodes of system A can have a higher capacitance and still be compliant to the standard. While the exact maximum ESD capacitance value will vary from system to system, Table 1 lists general capacitance and device recommendations for several popular high-speed interfaces.