Welcome back to the Get Connected blog series on Analog Wire! In the previous post, Interfacing between LVPECL, VML, CML, LVDS, and Sub-LVDS Levels, we took a closer look at how to convert between LVPECL, VML, CML, LVDS and Sub-LVDS interfaces using various techniques. In this post, I will cover equalization in general, and more specifically, the difference between a linear equalizer and a limiting equalizer.
Equalization
Equalization is a signal conditioning technique in which a waveform is manipulated at the transmitter, at the receiver, or by a signal conditioner somewhere throughout a link. Equalization compensates for distortions caused by channel impairments in systems that require high-speed signaling. In copper channels, the goal is to provide a flat frequency response up to the fundamental frequency by compensating the frequency dependent loss (ISI) of the linear time invariant (LTI) channel.
Transmit equalization is implemented in FPGAs, repeaters, redrivers, and in SerDes devices like the TLK10034 and the TLK10232. Transmit equalization pre-distorts a transmitted signal by either amplifying the high-frequency content or attenuating the DC portion of the signal to compensate for the expected amount of loss through the channel. The emphasized portion of the signal is attenuated by the channel, resulting in an open eye that can be easily interpreted by the receiver. Figure 1 shows an example of transmit equalization.
Figure 1: Transmit equalization
Equalization can be implemented in a receiver as well, to compensate for the loss that occurs after a signal travels through a channel, by restoring high-frequency content that was lost due to the channel attenuation. Figure 2 below shows an example of the effects of receive equalization when implemented in a 10Gbps serial link, transmitting 8b/10b data distorted by the channel.
Figure 2: Receive equalization
Transmit and receive equalization is used to effectively shorten the electrical length of a channel by providing an extra boost to the high-speed signal. When an equalizer is inserted in a channel, it provides the advantage of extended reach and/or more link margin, while also overcoming the bandwidth limitations of copper channels. If equalizers are injected into a channel, though, they have to work seamlessly in the system to provide low latency, low power and low cost.
Multi-stage continuous time linear equalizers or CTLEs are the most inexpensive, low-power option for these kinds of solutions, as their multiple stages can be adapted very well to the channel loss. Another advantage of CTLEs is that they are transparent to the link and do not require an external clock source, unlike a higher cost, higher power retimer solution. If the dynamic range of the equalizer is kept fully linear, the device can be called a linear equalizer. If a limiting amplifier is added during design after the CTLE stage, it is a limiting equalizer. The equalization process is linear in both devices.
Limiting Equalization
Limiting equalizers, such as the TLK1101E, have the advantage of restoring amplitude to a signal through the equalization stage so that the device transmitting or receiving the signal would not need to possess any equalization. Active copper cables in SFP+ connector designs are an option for these types of devices, but limiting equalizers are not a fit for all applications.
Equalizers that are 100% linear do not implement a limiting amplifier after the CTLE stage in the device. This provides an advantage over limiting equalizers in designs that require end-to-end equalization or link training. Linear equalizers reduce the effects of ISI, leaving the transmitted signal intact, so the end-to-end equalization or training sequences can be received unimpeded. Compared to a retimed solution, the latency of linear equalizers is negligible, and unlike retimers, they are transparent to auto negotiation and link training. TI recently introduced two linear equalizers: SN65LVCP1412 and SN65LVCP1414. Figure 3 below shows how a pre-distorted waveform is allowed to pass through the linear stages of these devices unchanged:
Figure 3: Input to SN65LVCP1414 / Output of SN65LVCP1414
For more information on solutions that implement linear equalizers, please visit the high speed interface forum in the TI E2E™ Community and check out existing posts from engineers already using TI’s interface products or create a new thread to address your specific application.
Please join me for my next post in the Get Connected series, where we will discuss general-purpose link aggregators and the applications they might work in.
Leave your comments below if you’d like to hear more about anything mentioned in this post or if there is a topic you'd like to see us tackle in the future!
And be sure to check out the full Get Connected series!
