Get Connected: Interfacing between LVPECL, VML, CML, LVDS, and sub-LVDS levels

Welcome back to the Get Connected blog series here on Analog Wire! In the previous Get Connected blog post, SerDes XAUI to SFI design, we took an in-depth look at using the TLK10232 in a XAUI to SFI protocol converter design. In this post, we are going to take a step back and examine how to convert between LVPECL, VML, CML, LVDS, and sub-LVDS interfaces.

Systems today are comprised of various interface standards such as CML and LVDS. Understanding how to properly couple and terminate transmission lines for serial data channels or clocking channels is a critical skill. Let us begin by examining the voltage levels and the required termination techniques for the most common interfaces:

Figure 1: Common Interface Voltage Levels

Figure 2: Common Interface Terminations

The voltage levels between the interfaces are not common and the interfaces require different terminations making one interface incompatible with the next. This is not a problem, though, as a work around solution exists to solve this problem.

In order to connect two different interfaces successfully, AC coupling capacitors must be placed in between the two interfaces. These AC-coupling capacitors strip away the DC component of the transmitted signal and allow for a new DC bias point or common mode voltage to be set. I typically place my AC-coupling capacitors and termination network as close to the receiver as I can get it to help avoid any transmission line effects, but the AC-coupling and termination can also be set next to the transmitter if you are designing a system in which you have no control over the receiver.  

When choosing the value of the AC-coupling capacitor, care should be taken as the capacitor should not fully charge before the bit period is over. Typical values for AC-coupling capacitors will be in the 0.1-uF to 0.01-uF range, but when in doubt calculate the RC time contact, Tau, and double check it against the bit time. When AC coupling, it is also important to have a DC-balanced data pattern as long runs of consecutive 1’s and 0’s will cause the capacitors to saturate or discharge completely which can cause bit errors on the proceeding bit transitions.  

I give two examples below in Figure 3 that show how to implement AC-coupling between a CML driver, LVPECL driver and a LVDS receiver.

Figure 3: Interconnecting Different Interfaces

This same approach can be used when connecting any two interfaces that differ, so long as the driver and receiver are terminated properly and AC-coupling capacitors are used.

A common question that I get is, “can I convert the output of a standard LVDS driver to support a sub-LVDS receiver?” The answer to this question is “yes,” and I will use the IBIS for the SN65LVDS100 and Hyperlynx to show how:

Figure 4: LVDS to Sub-LVDS Termination Scheme

Figure 5: Transmitted LVDS Waveform

Figure 6: Received Sub-LVDS Waveform After Termination

In this final example, we did not have to use AC-coupling capacitors to reset the common mode voltage as the ration of R1 to R3 and R2 to R4 sets the amount of attenuation applied to the common-mode signal. AC-coupling is still an option at this point though, if the sub-LVDS receiver requires it.

For more information on specifics between LVPECL, VML, CML, LVDS, and sub-LVDS interface application solutions, please visit the High Speed Interface Forum in TI’s E2E™ Community and check out existing posts from engineers already using TI interface products, or create a new thread to address your specific application.

Please join me for my next post in the Get Connected series where we will be discussing the differences between a linear equalizer and a limiting equalizer. If you are not connected, you can get connected with one of the broadest Interface portfolio’s in the industry. 

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