Get Connected: LVDS for multipoint applications

Other Parts Discussed in Post: SN65MLVD204B, SN65MLVD040, SN65MLVD206

Welcome to the fifth installment of the Get Connected blog series here on Analog Wire! In my previous post we explored some techniques for measuring random jitter and the components of deterministic jitter in the lab. In this post, we will discuss MLVDS, similar standards, and describe a practical MLVDS application.

When thinking of the possible architectures that one can have in a communication link, three topologies come to mind: point to point, multidrop, and multipoint. TIA/EIA-644, or LVDS, was created to provide a general purpose electrical layer specification for drivers and receivers in a point-to-point topology. A point-to-point topology is a half-duplex link that consists of a single driver and receiver with a differential termination. Figure one below shows a point-to-point configuration:

Figure 1: Point to Point

The next architecture is the multidrop topology. The LVDS standard was not developed with a multidrop topology in mind so the TIA/EIA-644 standard was updated in 2001 to support multidrop in the TIA/EIA-644-A (LVDS, REV-A) standard. The updated TIA/EIA-644-A standardized the driver requirements to limit the differential input leakage current of the LVDS receivers to 6 uA. A multidrop half-duplex link consists of a single driver communicating with multiple receivers using a termination resistor located away from the driver at the far end of the link. Figure 2 below shows a multidrop configuration:

Figure 2: Multidrop

The third architecture is the multipoint topology which requires an already developed TIA/EIA-899 (MLVDS) standard. Multipoint is a half-duplex link that consists of many drivers and many receivers all on the same bus with termination resistors located at either end of the bus. The double termination is necessary in this topology to support drivers located at various points throughout the transmission line.  Since both of these termination resistances are connected in parallel, the effective resistance seen by the multipoint driver is just 50 Ω (rather than the 100 Ω used in LVDS applications).  Accounting for additional loading from multiple transceivers sharing a bus, the driver loading can be as low as 30 Ω.With this decreased load, MLVDS drivers provide a typical differential output voltage of 565 mV, which is greater than the maximum differential voltage that LVDS drivers are required to support, and they nearly double the amount of short circuit current provided from 24 mA to 43 mA. Since there are periods when there are no active drivers on a bus segment, the common mode voltage of the circuit is gated by the attached components which can cause a larger than normal shift in common mode offset voltage. The MLVDS standard allows for ±1V ground noise offset which permits the common mode voltage range for MLVDS circuits to vary from -1V – 3.4V instead of the 0 – 2.4V common mode voltage supported in LVDS circuits.

Another concern in multipoint applications is long stubs off of the main transmission line, which can cause signal integrity nightmares for designers. General guidelines suggest that stubs be kept as small as possible, specifically speaking it is recommended that stubs be kept to 30% of a signals transition time. To combat this, MLVDS allows for edge rate control specifying that the minimum transition time be no less than 1 ns. This 1 ns transition time means that the maximum signaling rate expected in an MLVDS system is 500 Mbps, but stubs can reach almost two inches without violating the 30% guideline. Figure 3 below shows a multipoint configuration, and Table 1 below summarizes the differences between LVDS and MLVDS outlined above:

Figure 3: Multipoint

Table 1

The SN65MLVD204B and SN65MLVD040 are half-duplex MLVDS transceivers designed to support loads that range from 30 Ω to 55 Ω and signaling rates up to 200 Mbps and 250 Mbps respectively. Figure 3 below depicts a typical application where the MLVDS is used. In this scheme the SN65MLVD206 is used to distribute a synchronous clock from a main system clock via the systems backplane to the NPU, ASIC, FPGA, etc. Two SN65MLVD040 devices are used per line card to handle a 16-bit-wide data bus communicating over the backplane to another point in the system. It is easy to see why the TIA/EIA-899 standard was developed and why MLVDS makes sense for applications like the one below in Figure 3:

     

Figure 4: Typical MLVDS application

For more information on specific MLVDS application solutions, please visit the High Speed Interface Forum in TI’s E2E™ Community and check out existing posts from engineers already using TI interface products, or create a new thread to address your specific application.

Please join me for my next post in the Get Connected series where we will be discussing SerDes which are used to serialize low speed parallel data links into high speed differential links and vice versa. If you are not connected you can get connected with one of the broadest Interface portfolio’s in the industry. 

Leave your comments in the section below if you’d like to hear more about anything mentioned in this post or if there is a topic you'd like to see us tackle in the future!  

And be sure to check out the full Get Connected series! 

Anonymous