Welcome back to the Get Connected blog series here on Analog Wire! In the previous Get Connected blog post, SerDes Interfaces, we examined the OSI model and the different layers that make up the internal data path of a SerDes. In this post, we will discuss a specific SerDes application for 10-gigabit Ethernet (10GbE) designs, in which a low speed XAUI interface is converted to a high speed SFI interface through the TLK10232 dual-channel transceiver.
MAC to PHY interface
In my previous post, we showed from a high level that the OSI model is made up of a media access controller (MAC), a physical layer device (PHY), and the medium used to transmit the data. Figure 1 below recalls the OSI model:
Figure 1: OSI Model
The interface between a MAC and the PHY can take on many different forms and is dependent upon the intended standard the end application will support. For example, one of the interfaces that can exist between a MAC and the PHY layer is known as XGMII or 10 Gigabit Media Independent Interface, a parallel interface consisting of 74 wires (2 sets of 32 data, 4 controls and 1 clock). The XGMII is a cumbersome interface to work with though, which is why there are devices on the market such as the TLK3134.
XGMII to XAUI conversion
The TLK3134, known as a XGXS or XGMII extender, converts the 74 wires required by XGMII to 16 wires, which is a more manageable interface known as XAUI. However, the XGXS is an older standard interface and is being absorbed into both MAC and PHY devices by silicon manufacturers. This greatly reduces the need for extra chips to convert the XGMII to XAUI and significantly reduces the burden on the number of required electrical connections, which saves system designers both power and money.
The XAUI or 10 Gigabit Attachment Unit Interface consists of two sets of four lanes of differential data that is 8b/10b encoded, which negates the need for an additional clock line. Due to the amount of transition density present in the 8b/10b encoded data, an embedded clock can be recovered by the receiving device.
Converting XAUI to SFI
XAUI to SFI is a common conversion that takes four lanes of differential electrical data running at 3.125Gbps and converts it to a single electrical signal running at a data rate of 10.3125Gbps. SFI represents the high speed electrical interface for driving SFP+ optical modules and is governed by the SFF-8431 standard. SFI is another interface that can be used in the OSI model. However, instead of being a MAC to PHY interface, as discussed earlier, the interface is PHY to optical medium to PHY. Figure 2 below shows a typical application using the TLK10232 in a XAUI to SFI application:
Figure 2: TLK10232 Dual Channel Transceiver
In this design, the TLK10232 eliminates the need for the XGXS conversion, as it has a XAUI interface native to its architecture. The TLK10232 also supports multiple high speed interfaces through a selectable data path, including SFI, which can be setup through internal registers via MDIO. Figure 3 below depicts the data path through the TLK10232 that supports a XAUI to SFI application:
Figure 3: TLK10232 TX Block Diagram
Figure 4: TLK10232 RX Block Diagram
Designing with the TLK10232
TI assembled a XAUI to SFI Reference Design for the TLK10232, which can be leveraged by the end user for immediate system level implementation. The XAUI to SFI reference design enables quick integration of the TLK10232 PHY into designs that require an optical PMD layer with 10GbE PCS functionality. A multiport 10GbE network interface card or 10GbE NIC card is an example of a design that would meet these requirements.
TI conducted extensive system level testing for the XAUI to SFI reference design, which are included on the reference design website for download and evaluation. Figure 4 below shows the quality of the SFI compliant transmitter output eye versus the SFF-8431 transmitter eye mask requirement for the TLK10232 at 85°C.
Figure 5: TLK10232 Transmitter Output Eye Diagram 25°C
For more information on Ethernet specific PHY application solutions, please visit the High Speed Interface Forum in TI’s E2E™ Community and check out existing posts from engineers already using TI interface products, or create a new thread to address your specific application.
Please join me for my next post in the Get Connected series where we will be discussing how to convert standard interfaces such as LVDS and LVPECL to sub-LVDS or reduced swing differential signaling (RSDS). If you are not connected you can get connected with one of the broadest Interface portfolio’s in the industry.
Leave your comments in the section below if you’d like to hear more about anything mentioned in this post or if there is a topic you'd like to see us tackle in the future!
And be sure to check out the full Get Connected series!
