TI recently unveiled a couple of JESD204B digital-to-analog converters (DACs) that include a first-of-its-kind feature for high-speed, quad-channel DACs: the summation block. Located in the signal path after the interpolation filters and complex mixers, it enables two complex digital paths to be added together prior to conversion to analog.
What can I do with the summation block?
If you need to transmit two different frequency bands at the same time with one transmitter (imagine two different cellular bands serviced with a single, wideband transmitter), this feature is for you. The summation block offloads the burden of creating the frequency separation in the FPGA and puts that burden into the DAC.
Figure 1 shows four digital paths in the DAC38J84, labeled A, B, C and D. These can be treated as two complex paths – A-B and C-D. Both complex paths provide interpolation and NCO-based digital mixing, providing you with two digital block up converters in the quad channel DAC.
Figure 1: Diagram of DAC38J84 emphasizing the multi-band summation block in blue
When not using the summation block, these two up converters can be used independently to finalize data to DACs A and B for one transmitter and DACs C and D for another, assuming the quad DAC is followed by two complex modulators.
When using the summation block, you won’t need all four output DACs, just DACs A and B, so only one RF output path is served with an analog complex signal.
Let’s say we send a 1.2288GSPS, 1GHz wide, complex pattern to each of two complex data paths, which we will call ‘AB’ and ‘CD’, in the DAC38J84.
Each complex path interpolates by two, so the data rate after interpolation is 2.4576GSPS. With the NCO also running at this rate, you can tune the ‘AB’ data pair such that its entire 1GHz of information bandwidth is located in the 0 to +1000MHz spectrum by tuning the NCO to +500MHz.
You can then tune the CD data pair to -500MHz to place that spectrum from -1000MHz to 0Hz. Remember, you sent a complex pattern to two complex data paths. Using the digital summation block, you can then sum the AB and CD data paths together. They are still running at 2.4576GSPS but now have signal information in the complex spectrum from -1000MHz to +1000MHz, creating 2GHz of information bandwidth.
Now, you can send the combined data path to DACs A and B for analog conversion and transmit. This enables you to send 2GHz of information bandwidth into the analog/RF world with FPGA/DUC rates of only 1.23GSPS. This allows you to choose slower FPGA DUC rates, which eases FPGA design speeds and logic gate requirements, and lowers the FPGA-to-DAC38J84 interface speed, which also has the potential to reduce the FPGA costs by using a lower speed/cost FPGA.
If you’d like to see this concept in action, check out this video demonstration from my colleague Matt Guibord that explains how to achieve 2GHz of complex bandwidth with the DAC38J84.
I’ve provided one example of how to add two complex digital paths together before the analog conversion. How could you use this to benefit a different application?
Additional resources:
- Read the DAC38J84 datasheet
- Buy the DAC38J84 evaluation module (EVM)
- Learn more about TI’s portfolio of JESD204B analog-to-digital converters (ADCs), DACs and clocks
