If you have anything to do with high-speed data capture designs using an FPGA, you’ve probably heard the new buzz word, ‘JESD204B’.
In my role here at TI, I’ve seen a lot of engineers request information on the JESD204B interface and how it works with an FPGA. They’re especially curious about how it will make their design life easier.
The JESD204B serial interface standard for data converters provides some significant benefits over LVDS and CMOS interfaces. This includes easier layout and reduced pin-count. It’s no wonder it’s gained popularity and the attention of engineers with system-level benefits like these:
- Reduced package size and cost: JESD204B serially packs data with 8b10b encoding and helps support data rates up to 12.5Gbps. This drastically reduces the number of pins needed on the data converter and FPGA, which helps reduce package size and package cost.
- Simplified PCB layout and routing: Reduced pin count significantly simplifies PCB layout and routing, since there are fewer lanes on the board. The layout and routing is further simplified, since there is a reduced need for skew management. This is because the data clock is embedded in the data stream, combined with the elastic buffer in the receiver, eliminates the need for ‘squiggles’ to match lengths. Figure 1 shows an example of how considerably the JESD204B interface helps simplify PCB layout.
- Flexible layout: JESD204B allows longer transmission distances because of relaxed skew requirements. This enables logic devices to be placed much farther from the data converter to avoid impact on sensitive analog parts.
- Future proof: The interface is adaptable to different data converter resolutions, removing the need for physical redesign of TX/RX boards (logic devices) for future analog-to-digital converters (ADCs) and digital-to-analog converters (DACs).
Figure 1: PCB Layout with LVDS DAC (left); PCB Layout of the same DAC with JESD204B (right)
Does this mean you should switch to the JESD204B interface?
Not necessarily. The drawback of JESD204B over the LVDS interface is that the longer absolute latency might be unacceptable for some applications.
While JESD204B provides many benefits, there are applications that require minimal latency – in an ideal world, no latency. A great example is a signal jammer used in in electronic warfare. This equipment requires absolute latency and a need to minimize any possible delay.
For applications like this, you should consider the LVDS interface, since the delay in serializing the data on JESD204B is omitted.
If you’d like to learn more about JESD204B, here are some additional resources:
- For a more in-depth look at the evolution of the JESD204B interface and its characteristics check out my technical article, “When is the JESD204B interface the right choice?”
- Check out this blog post, “JESD204B vs. LVDS in high speed data converters,” from my colleague Rick Zarr.
- Learn more about TI’s JESD204B portfolio, including the 12-bit, 4-GSPS ADC12J4000 analog-to-digital converter (ADC); 16-bit, dual, 250-MSPS ADS42JB69 ADC; 16-bit, 4-channel, 2.5-GSPS DAC38J84 digital-to-analog converter (DAC) and LMK04828 high-performance clock jitter cleaner.
- Check out our latest JESD204B blogs.
JESD204B definitely makes it easy for the chip designers and the FPGA designers in many applications. System designers should take note that there is a penalty to be paid in power/cost and some customers…