I remember when a 12-bit ADC had 12 LVCMOS data lines and a clock pin to tell your logic when to sample the lines. Oh the simplicity of those days… but I digress. Progress after all is to make things better, faster more powerful and all that jazz. As we have continued to improve the performance of analog-to-digital converters (ADCs), the industry has struggled with the amount of data these devices produce – both in the transmission of the data and the consumption.
For example, the ADC12D1600 is a 12-bit dual 1600 MSPS ADC. It has 48 LVDS matched pairs for data producing at full speed roughly 267 megabytes of data every second. Routing the 96 transmission lines (not including the clock) can be challenging since they all must be electrically matched in length (delay). As converters (both ADCs and DACs) have continued to get faster with increased resolution, this problem has become much worse.
Knowing this, the industry has decided (as it has on many bus structures such as PCI) to serialize the data and embed the data clock into the stream. This greatly simplifies the layout and the clock to data phase relationship. Enter the JEDEC standard JESD204 version B or simply JESD204B which is the latest of the JESD204 standards.
Figure 1: JESD204B serial interface significantly reduces the number of lanes, and the embedded output data clock eliminates the need for line bus matching to simplify the digital data interface and reduce board space.
The original ‘A’ standard defined connections speeds only to 3.125 Gbps per lane, but the newer ‘B’ standard allows for multiples of 3.125 Gbps all the way to 12.5 Gbps per lane. The ‘A’ standard also lacked the ability to phase align or synchronize multiple ADCs. This is extremely important for communications and instrumentation systems taking inputs from multiple ADCs that all must be phase aligned. This ability was added in the ‘B’ revision.
All in all, the comparison of LVDS to JESD204B is very similar to comparing PCI to PCI express… take a look at the following table for the ADS42JB69 dual 16-bit, 250 MSPS ADC and you decide!
Table 1: JESD204B vs. LVDS comparison
Laying out the PCB for the JESD204B interface is quite a bit easier and provides much more functionality. For instance, switching from a 14-bit ADC to a 16-bit ADC would use the same amount of lanes – components within families may even have the same pin-out. Phase aligning multiple ADCs is also much easier and requires less matching of critical lines.
So there you have it... my vote goes to JESD204B with simplified layout, sampling synchronization between multiple ADCs and lower pin counts! Till next time…
Oh, in case you’d like to read more on why JESD204B is the smart choice, check out these articles: