The top 5 questions when using M-LVDS in backplane applications
Multipoint low-voltage differential signaling (M-LVDS) is an established standard (Telecommunication Industries Association/Electronic Industries Alliance [TIA/EIA]-899) that allows for high-speed communication between as many as 32 devices. M-LVDS can be used in a backplane configuration as well as with cables. It is a popular choice for data interchange and clock distribution on backplanes.
M-LVDS differs from standard LVDS (TIA/EIA-644A) in that it provides an increased current drive to handle the higher load due to the double terminations required in multipoint applications. M-LVDS drivers use controlled transition times to minimize reflections that are common in multipoint configurations due to unterminated stubs. M-LVDS devices also have a large input common-mode voltage range for additional noise margin in heavily loaded and noisy backplane environments.
In this post, I will address the top five questions facing the designer when designing M-LVDS in a backplane arrangement, including some tips and practical design guidelines
1. How many transceivers can the backplane accommodate?
According to the M-LVDS standard, you can connect a maximum of 32 M-LVDS devices (transmitters, receivers, or transceivers) in an M-LVDS bus. This is based on the 20µA maximum leakage specification for receivers and disabled drivers/transceivers, which is equivalent to a 120kΩ minimum input impedance.
But is there a lower practical limit? It depends on how well your system is designed, including printed circuit board (PCB) layout, line impedance control, proper terminations, stub length and edge rates. It is possible to run a well-optimized backplane with 30 slots at >200Mbps.
2. What about stubs?
M-LVDS uses double terminations, one on each end of the bus. The plug-in boards on the backplane create stubs (unterminated transmission lines). These stubs create impedance mismatches on the bus, which could potentially create reflections. To minimize the effect of the stubs, they should be as short as possible.
Figure 1: Stubs generated by a plug-in board on the backplane
How short do the stubs need to be? The answers depend on the transition times. A general guideline is to keep the propagation delay of a stub less than 30% of the transition time. For example, if the minimum transition time is 1.5 ns, the stub length should be less than 0.5 ns. This means that for FR-4 PCB material (with approximately one ns of propagation delay per 6 inches), the stub length should be less than 3 inches.
Please notice, however, that the 3-inch stub length mentioned above is a maximum. You should minimize the stub length as much as possible; in general, a stub length less than 1 inch is recommended. A shorter stub length would be even better, as it leads to higher noise margins. Shortening the stubs from 1 to .5 inches may increase the noise margin by as much as 50 percent.
Make sure to include the length of the connector in the stub length. Also, watch for unintended stubs created by test points on the differential lines. You should account for these stubs and minimize their length.
3. How do you select the line characteristic impedance in a heavily loaded backplane?
You will generally need to design the characteristic impedance of the interconnect to be higher than 100Ω so that when the bus is loaded, the effective characteristic impedance of the line stays above 80Ω.
M-LVDS drivers can drive loads as low as 30Ω. The loading from the devices on the bus (transmitters, receivers, or transceivers) lowers the overall effective impedance of the bus due to the capacitance of the stub and the input/output (I/O).
The characteristic impedance of the interconnect should be designed to be higher than 100 Ω, so that the effective characteristic impedance of the line is between 80Ω to 100Ω with the loading of the stubs and I/Os. For a heavily-loaded backplane with close slots, simulations and experiments indicate that a line characteristic impedance of 130Ω works well to account for stub and I/O capacitive loading.
Notice that if the effective impedance of the line is lower than 100Ω, you may need to lower the termination resistance to maintain impedance matching and reduce reflections.
Also, make sure to evenly space loads on the backplane (plug-in cards) in order to help evenly distribute the loading and reduce irregularities. Notice that decreasing slot pitch (the distance between plug-in boards) increases the effective loading, which reduces the effective backplane impedance. A slot pitch of around 0.8 inches works well with the 130Ω line impedance.
4. Where should you locate the drivers and receivers on the backplane?
If you have a choice of where to place drivers and receivers on the backplane, avoid placing drivers in the middle of the bus. Placing drivers toward the two ends of the backplane leads to a longer signal path on average, which slows down the rising and falling edges. Slower transition times are less susceptible to discontinuities and impedance mismatches on the bus.
5. When do you use Type-1 and Type-2 receivers?
The threshold of Type-1 receivers is centered on 0V (-50mV to 50mV), while the threshold of Type-2 receivers is centered on 100mV (50mV to 150mV). See Figure 2.
Figure 2: Differential input voltage thresholds for Type-1 and Type-2 receivers
Type-1 receivers can support higher M-LVDS data rates when compared to Type-2 receivers, due to higher noise margins. Use Type-1 receivers for applications that require higher data rates or clock frequencies.
Use Type-2 receivers when you need to support fail-safe operation. The output of a Type-2 receiver is a known logic low state when the bus is not driven (0V differential voltage). Also, use Type-2 receivers when you need to support Wired-OR logic, where outputs from multiple drivers are tied together. In this case, the input signal is fed to the enable (EN) input of the drivers, while the data input (D) of all drivers are tied high. See Figure 3.
Figure 3: Using the wired-OR feature with a Type-2 M-LVDS receiver
In conclusion, M-LVDS is a good option for high-speed data and clock distribution on backplanes. The designer must carefully follow good design practices to ensure successful implementation of M-LVDS. In this post we addressed some of the top issues facing the designer when using M-LVDS in a backplane.
- Read these application reports:
- Read the Analog Applications Journal article,Maximizing signal integrity with M-LVDS backplanes
- Download the LVDS Owner's Manual