Timing is Everything: I need a clock, can you help?

Welcome back to our Timing is Everything clock series! Today I will be covering how to select the clock or timing IC that best fits your application.

It’s a fair question to ask: “Is there more to choosing a clock than to just pick one that produces the frequency I want?” For me, that is definitely a very important question, but the more you learn about clocks, the more you will realize that there is an extraordinary list of features and capabilities for different clocking devices, and a careful selection process can be very rewarding.

For example, selecting the right clock can extend your range in a wireless device, maximize the quality of your data, reduce the size and complexity of your products and much more.

The best approach for selecting your clock is to know the key features associated with each type of clocking product. 

Phase locked loop (PLL) / synthesizer

At the core of every clocking device is the PLL, which in using a negative feedback control loop, can lock to a reference frequency and output a filtered version of the signal at a multiple of that frequency. In the industry, there is a differentiation for a synthesizer (has phase frequency detector, low pass filter, charge pump, voltage controlled oscillator and feedback network) and a PLL (synthesizer minus the VCO). There are also integer types (produce integer multiples of reference frequency) and fractional types (capable of producing decimal multiples of the reference frequency). It is essential to first identify up to what frequency the device can accept at the input and what the range of output is. Then, pay close attention to some key specifications like 1/f noise, PLL flat noise and VCO open loop phase noise. PLLs/synthesizers are a great fit for wireless infrastructure, test and measurement equipment, satellite and military radar applications.

Generator

Building on a PLL, the generator can distribute the signal from your PLL to many more sources that need clocking. Each output of the generator usually also has dividers so you can have multiple outputs configured to your desired frequency. Many features of a good generator are low RMS jitter and phase noise, universal input/output, flexible frequency plan, differential/single end, crystal or XO input, fractional and integer dividers and programmability. Also, pay attention to what types of clocking signal the generator can provide. For example: single/differential ended, sine/square wave, LVCMOS, LVPECL, LVDS, or HCSL. Clock generators address applications such as high speed interface, multi-gigabit Ethernet, data conversion, DSPs, microprocessors and FPGA clocking.

Jitter cleaner

Using an additional PLL, the jitter cleaner essentially uses two sets of filtering aimed at minimizing the phase noise. With a good jitter cleaner, you can achieve very low RMS jitter and phase noise, programmable outputs, high max clock frequency and one or two integrated VCO. Clock jitter cleaners are ideal for data converter clocking, wireless infrastructure, networking, medical, video and military and aerospace applications.

Buffer

In the timing realm, buffers are often needed for various purposes in interfacing with clocks. To choose one that fits you, look for low additive jitter, universal inputs, high max clock frequency, high PSRR, low output skew and a programmable divider. Clock buffers can be used in many applications, including wireless infrastructure, datacom and telecom clock distribution, medical imaging, test and measurement and military and aerospace.

Choosing a clock can be simple if you know their features and benefits and what they bring to different applications. Although there are a number of choices that can give you a functional solution, selecting a better clock can significantly improve the performance of your system and deliver many features that can benefit your application. Hope this blog is useful, and good luck with your design!

Thanks for joining me for Timing is Everything. Check out other blogs in this series, including Understanding PLL loop filter response.

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