Welcome back to Timing is Everything! Last time in our series, we covered how to measure additive jitter. Today, I will be discussing phase lock loop (PLL) systems and how to understand PLL loop filter response. A PLL system consists of a stable and clean reference clock, a PLL device, and a loop filter followed by a voltage-controlled oscillator (VCO).
Figure 1: Typical PLL system block diagram.
Determining the design of a PLL usually means also determining the design of the loop filter, which affects aspects of loop performance. Many find it difficult to optimize the loop filter because there are several variables in the loop, such as phase noise, lock time and spurs, which have to be taken into account during the design. However, a PLL design is not as difficult as it appears to be. As long as we understand the loop filter response on each noise contributor in a PLL, we know how to make an optimum PLL design.
There are four major noise contributors in a PLL: the reference clock, the PLL device, the loop filter and the VCO. Let’s take a look at these noise contributors and how the loop filter responds to each noise contributor:
The reference clock
The loop filter’s response to the reference clock is low pass. As a result, the reference clock phase noise after the loop bandwidth is reduced.
Figure 2: Reference clock phase noise. Original (left), after loop filter (right).
The PLL device
The loop filter’s response to the PLL device is also low pass. The smaller the loop bandwidth, the more PLL noise is reduced.
Figure 3: PLL device phase noise. Original (left), after loop filter (right).
The loop filter
In most cases, we use a passive loop filter because it is low cost and easy to implement. The loop filter’s response is somewhat band pass with the peak appearing at the loop bandwidth. The phase noise comes from the thermal noises of the resistors.
Figure 4: Passive loop filter phase noise.
The VCO
The strangest thing in a PLL design is that the loop filter’s response to the VCO is high pass. This is contradictory to the reference clock as well as the PLL device. As a result, we cannot use an ultra-wide or ultra-narrow loop filter for all designs. We have to optimize the loop bandwidth to a point where it trades off between these noise contributors.
Figure 5: VCO phase noise. Original (left), after loop filter (right).
Total phase noise and optimization
In a phase lock loop system, the total phase noise is the summation of the previously mentioned noise contributors. From the plot in Figure 6 below, we can easily separate total phase noise into three regions: the reference clock, the PLL device and the VCO.
Figure 6: Total phase noise
The loop filter can do nothing to improve the phase noise in the reference clock region or the VCO region. The only way to reduce this phase noise is to use a better reference clock and to choose a better phase noise VCO.
The PLL device noise region is made up of 1/f noise, PLL flat noise and N-counter noise. 1/f noise and PLL flat noise are charge pump current dependent. These noises are lower with a higher charge pump current. The N-counter will add 20log(N) to the PLL device noise; therefore, it is desirable to have a smaller N-counter value. (See figure 7 below.)
Figure 7: PLL device noise. 1/f noise and PLL flat noise (left), N-counter increases noise (right).
Now that you understand the loop filter response on each noise contributor in a PLL, you are prepared to make an optimum PLL design. However, if you need a little help when selecting and optimizing the loop filter: use our Clock Design Tool to do loop filter simulations or use the WEBENCH Clock Architect to find out the complete clock tree solution and simulation.
Thanks for joining me on Timing is Everything! Please leave any questions or comments about material covered in this post below, or head to the Clock and Timing Forum in TI’s E2E™ Community to get your specific application need or question addressed!
