High-gain, high-bandwidth…why is this circuit oscillating?

Last week we looked at achieving both high gain and wide bandwidth while maintaining sufficient signal-to-noise ratio (SNR) in “High-gain, high-bandwidth…how can I get it all?” In this post, we will look more closely at the implementation and what can go wrong.

Since the target gain is very high, the first thing to look at is the direct-current (DC) operation to verify whether the output offset voltage is within expectations.  If it’s beyond what is expected from the gain stages and the amplifier’s DC parameters, input bias current and input offset voltage, then the circuit may simply oscillate.  An oscillation in a system can appear in many forms, such as increased noise, output offset voltage, and increased quiescent current when no load is present, to name a few.

If an oscillation is present and the circuit is DC coupled with high gain and each stage is operating nominally, the alternating current (AC) coupling each stage will remove the output offset voltage as a potential issue.  Now the only task left is to eliminate the undesirable feature.

Oscillations occur when there is a positive feedback loop, or when the phase margin of a system is reduced.  Since the amplifier by itself is stable and the load is resistive, this only leaves the positive feedback loop option.

The circuit, shown below in figure 1, handles large DC offset by shaping the amplifier noise gain at low frequencies.  From this, any DC component will only have a gain of 1-V/V to the output.  Figure 1 also shows the power supply connected through a power plane.  The local power supply bypass capacitor for each amplifier is included, but the global power supply bypass capacitors were left out for simplification.

Figure 1: Multi-stage amplifier schematic with power plane

Now consider that the last stage is driving a heavy load, the current will flow from the power supply into the load.  The current will create a disturbance on the power supply rail.  Since the rails of the multi-stage amplifier are connected together, the disturbance will be visible in the first and second stage.  That disturbance will appear at the output of the first stage attenuated only by the power supply rejection ratio (PSRR) of that first stage and then gained up by the signal gain of the second and third stages.

If the PSRR at the disturbance frequency is lower than the product of the second and third stage gain, the disturbance generated in the load will be amplified.  In other words, there is a positive feedback loop on the power supply rail.

This can be resolved simply by being careful in the board layout and powering the last stage first and inserting an inductor in series between each stage.  For the three stage amplifier shown below, we will add only two inductors on each power supply.  This implementation is represented in figure 2 for the positive supply.  Note that this may be required on the negative supply as well.

Figure 2: Implementation of the power supply isolation between stages

The example developed in figure 2 uses the LMH6629 for the first stage and the OPA684 for both the second and third stages. 

Good bandwidth flatness is achieved to 5MHz with a -3dB bandwidth right at 10MHz operating on a +5-V supply, see figure 3.  For a 10uV signal and an amplification of 100,000V/V, the resulting SNR is ~12dB.

Figure 3: Frequency response after each stage

  • Hello Xavier,

    This information was so valuable for me as I designed high-gain wideband amplifiers. I designed fully differential amplifiers with a voltage gain between 70 and 90 dB for the frequency bandwidth between 100 to 500 MHz. There are 4 stage open loop amplifiers without closed loops to remove the probability of the oscillation with a gain of approximately 20 dB. Only in the first and third stages, I put resistors to make a self-bias transistor to remove the necessity of the bias circuits. I simulated it on Cadence, and in the transient analysis, I couldn't see any oscillation. However, I now measure the fabricated chip, and it is oscillating. The only close loop between the input and output nodes can be found in VDD and GND nodes. Also, I should make it clear that the VDD of the first stage has been separated in the layout from other stages' VDD, although the GND nodes of every stage are connected internally (inside of the layout).

    Would you please let me know if this oscillation can occur due to the GND? Is there any other scenario for oscillation?


  • Michael,

    You are correct a resistor could be used.  Its onlly drawback is the headroom reduction in the power supply, which would be minimal in this case.

    A follow-on article, to be published shortly, will show the layout used to evaluate this circuit.

    Best regards,


  • Robert,

    I do not believe a 'star point' approach would work in this case as the signal chain has too much gain in it.  The PSRR of the first amplifier will not be sufficient, so the argument remains the same unless you plan to introduce inductors after the star connection.  It would work just as well for a 2 or 3 stage amplifier.  Above 3 stage, I would expect some possible degradation.  Note that the last stage would have to be driving a light load as well as an inductor would have to be in series in the power supply.  If a heavy load were to be driven, that last stage inductor would create problems by modulating the power supply with the load.

    Best regards,


  • Ben,

    Thank you for your comment.  In the physical implementation, we selected a 1uH inductor, the 1mH is an error and should be corrected shortly.

    My understanding of ferrite beads is that they are low Q inductors and can have heat losses associated with them.  It is also easier to achieve higher value due to the ferrite core used.

    In this instance, due to the use of high-speed amplifier, resulting in a relatively high frequency roll-off of the PSRR, coupled with a relatively large bypass capacitance at its supply pins, a low value inductance can be used and, in my mind, does not require the use of a ferrite bead.

    Best regards,


  • Couple comments:

    Large value (1mH) inductors usually have self-resonant frequency within BW of interest (Fig. 3).

    Star power connection (mentioned by Robert Dixon) along with small (few uH)  inductors and ~10uF ceramic capacitors capacitors would be safer. 10-50 Ohm resistors instead of inductors should work as well.

    The article should have mentioned importance of the layout.