Last week we looked at achieving both high gain and wide bandwidth while maintaining sufficient signal-to-noise ratio (SNR) in “High-gain, high-bandwidth…how can I get it all?” In this post, we will look more closely at the implementation and what can go wrong.
Since the target gain is very high, the first thing to look at is the direct-current (DC) operation to verify whether the output offset voltage is within expectations. If it’s beyond what is expected from the gain stages and the amplifier’s DC parameters, input bias current and input offset voltage, then the circuit may simply oscillate. An oscillation in a system can appear in many forms, such as increased noise, output offset voltage, and increased quiescent current when no load is present, to name a few.
If an oscillation is present and the circuit is DC coupled with high gain and each stage is operating nominally, the alternating current (AC) coupling each stage will remove the output offset voltage as a potential issue. Now the only task left is to eliminate the undesirable feature.
Oscillations occur when there is a positive feedback loop, or when the phase margin of a system is reduced. Since the amplifier by itself is stable and the load is resistive, this only leaves the positive feedback loop option.
The circuit, shown below in figure 1, handles large DC offset by shaping the amplifier noise gain at low frequencies. From this, any DC component will only have a gain of 1-V/V to the output. Figure 1 also shows the power supply connected through a power plane. The local power supply bypass capacitor for each amplifier is included, but the global power supply bypass capacitors were left out for simplification.
Figure 1: Multi-stage amplifier schematic with power plane
Now consider that the last stage is driving a heavy load, the current will flow from the power supply into the load. The current will create a disturbance on the power supply rail. Since the rails of the multi-stage amplifier are connected together, the disturbance will be visible in the first and second stage. That disturbance will appear at the output of the first stage attenuated only by the power supply rejection ratio (PSRR) of that first stage and then gained up by the signal gain of the second and third stages.
If the PSRR at the disturbance frequency is lower than the product of the second and third stage gain, the disturbance generated in the load will be amplified. In other words, there is a positive feedback loop on the power supply rail.
This can be resolved simply by being careful in the board layout and powering the last stage first and inserting an inductor in series between each stage. For the three stage amplifier shown below, we will add only two inductors on each power supply. This implementation is represented in figure 2 for the positive supply. Note that this may be required on the negative supply as well.
Figure 2: Implementation of the power supply isolation between stages
Good bandwidth flatness is achieved to 5MHz with a -3dB bandwidth right at 10MHz operating on a +5-V supply, see figure 3. For a 10uV signal and an amplification of 100,000V/V, the resulting SNR is ~12dB.
Figure 3: Frequency response after each stage