What do CAN bus signals look like?

Welcome to the second post in this series on the controller area network (CAN), which is increasingly being used in industrial applications. In this post, I’ll focus on the signaling levels found on a CAN bus, so that designers will understand the origin of CAN’s reputation for noise immunity.

As stated in my first post, CAN is a serial, two-wire, differential bus technology. This means that data is sent one bit at a time through two complementary signals on the controller area network high (CANH) and controller area network low (CANL) bus wires.

To effectively explain the different types of signals, it’s useful to first understand a typical CAN application. Every CAN application consists of a microcontroller with built-in CAN controller and a transceiver that is tied to the bus. A discrete implementation of this is shown in Figure 1. The two types of signals that are processed by the CAN transceiver are single-ended signals (TXD and RXD) and differential signals (CANH and CANL). During normal operation, the CAN transceiver converts the single-ended logic-level output signal (TXD) from the CAN controller to a differential signal. It also converts the differential signal on the bus back to a single-ended logic signal (RXD) for input into the CAN controller. Essentially, the transceiver provides differential drive and differential receive capability to and from the CAN bus.

Figure 1: CAN controller and CAN transceiver


The CAN bus has two logical states: dominant and recessive. The dominant state occurs when a logic low level is applied to the transmit input pin (usually called TXD) of the transceiver. The recessive state corresponds to a logic high level on the transmit input pin of the transceiver. Figure 2 shows these two states.

Figure 2: CAN bus signal levels


As you can see, in the recessive state both the CANH and CANL bus pins are biased to the same level: ~2.5V. During the dominant state, the CANH bus pin is biased to a higher voltage potential (~3.5V) and the CANL bus pin is biased to a lower voltage potential (~1.5V). By subtracting the voltage potential of the two bus pins, you can determine the logical state of the bus using Equation 1. When the Vdiff value on the bus is less than 0.5V, the bus is considered to be in a recessive state. Alternately, Vdiff values greater than 0.9V indicate that the bus is in a dominant state. Lastly, for Vdiff values between 0.5V and 0.9V, the bus state is undefined. Since the difference between the two signals is used to define the state of the bus, this signaling type is known as differential signaling. Additionally, the CANH and CANL signals are commonly referred to as complementary singles since you need to know the voltage potential of both signals to determine the logical state of the bus.


The recessive state will only exist on the bus if all transceivers connected to the bus are transmitting a recessive state, because the recessive state is weakly biased, while the dominant state is strongly biased. This is analogous to a wired logical AND connection. All transceivers must be transmitting a logical high signal for the bus output to be logical high. If even one transceiver transmits a logical 0, the entire bus will follow this state and will be in the dominant state.

Now that you know what the differential bus signals on a CAN bus look like, stay tuned for my next post which will describe the typical driver topology that is used to create these bus signals. Feel free to post any questions or comments below. 

Additional resources:

  • Hi Naveen,

    CAN is an asynchronous communication standard. This means that there is no clock that is transmitted on the bus. Therefore, since each CAN node then has their own local clock source, they need a way to synchronize. This synchronization only happens on a recessive to dominant edge of the bus since this is the actively driven edge and is a much cleaner signal to sync on.

    For an extreme example, if you were to send 8 bytes of of all 1's or all 0's there would be at least 64 bit times with no synchronization. With clocks possibly drifting in opposite directions this could cause timing issues with clocking in the correct data. This is why bit stuffing was added to the standard. It ensures that a maximum of 5 consecutive bits of the same polarity will ever be sent on the bus. 

    Hope that helps,


  • Hi John,

    can you explain the significance of bit stuffing? It is quite confusing for the fact that in serial  communication, bit by bit transmission is happening which means a voltage signal of relavant logic level (for bit 0 and 1) is being sent on the bus each time. basis this understanding what is the need of bit stuffing?..

  • Hi Michael,

    The recessive, or not active state for controller area network (CAN), is logic high. Sometimes I think this should be the opposite but its not! :D 

  • Hello. When the instrument panel is powered, On my transceiver, on its TXD and RXD pins, 5 V is always present.  Accordingly, the instrument panel does not turn on and is silent. VCC is also 5 V. On the CAN-H and CAN-L there is a 2.5 V recessive relative to the GND. The question is, why is there 5 V on the TXD and RXD pins? Is the transceiver faulty and needs to be replaced? The line is not communicating. Thank you!

  • Hi Nihadh,

    I agree, the way the standard designated the logic levels for TXD and RXD could have been switched (logic high as dominant and logic low as recessive) and it might have made more sense but this is just how Bosch defined the logic levels originally.  All the following updates to the standard (including ISO 11898 versions we use today) have kept the same polarity to be backwards compatible. 

    Hope this helps,