Engineer It Video Series: Testing Power Supplies


Let's talk about it!

The Engineer It videos from Texas Instruments are instructional, how-to videos on a variety of technical topics. We've devoted this space to talk about a series of Engineer It videos devoted to testing power supplies. The four-part video series featuring TI's Bob Hanrahan describes how to properly test a DC/DC power supply, and ensure that it works reliably over various operating conditions. This series is intended to provide the designer with a sufficient understanding about the testing needed to verify a reliable power supply design. Share your thoughts and questions here.


Engineer It: Testing Power Supplies with Bob Hanrahan

Part 1: Overview

Part 2: Measuring Efficiency

Part 3: Measuring Noise

Part 4: Measuring Stability

Were these videos helpful? Do you have further questions? Is there additional material on this topic you would like to see covered? 

Let's talk about it!

 

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  • Hi,

    Thanks for a very clear and informative videos!

    In the part 2 you speak about the design problems we can find with the help of efficiency plot. Can you possibly give an example of such a problem?

    Best regards,

    Yura

  • Hello,

    I really appreciated these videos.  They presented information on power supply characterization in an exceptionally practical and helpful manner.  I look forward to viewing further videos from this contributor.  Thank you.

  • Yes these video's were very helpful and should be implemented thoroughly over all TI's component portfolios.

  • Thanks very much for all the nice comments, I appreciate the feedback and am very glad to hear that the material was beneficial.

    Yura:

    A few examples of problems that I discovered with an efficiency graph are as follows.  When a power supply starts going into current limiting you will see a sharp change of slope with a fairly linear down-turn as the voltage drops off.  Sometimes people miscalculate and find that the peak switch current is higher than they figured, especially in a boost converter design.  Once you see the spot where the slope changes you can study that specific condition.  Another example is where a power circuit goes unstable.  Most often when a power control loop is even marginally unstable the efficiency will suffer.  This is again shown by an abrupt change in slope of the graph, sometimes only with specific input voltages and output currents.  Again the graph will pinpoint the conditions where the problem exists; often a look at the switch node waveform will show some instability (jitter or unexpected oscillation).  Instability can be caused by many things, yet if it's simply a marginal control loop, the measurements explained in part 4 of this video series, or in part 3 of the EDN series on the subject should help.

    Thanks for the question!  Bob

  • Nice video. it's really helpful for the flash engineers who designs the power supply.

  • Hi Bob,

    This is a great set of video tutorials on power supply testing.  Thanks.

    I have a few questions regarding power supply stability measurements:

    1. How much phase and gain margin is acceptable for a power supply?

    2. How can I test the stability of an LDO that does not have external feedback components?  I recently encountered one that was unstable at low temperatures.  I seek a method to determine the control loop margin to predict this possibility.

    3. Can a step load response be used to determine stability?

    Thanks,

    Jeff

  • Hi Jeff,  Thanks for the questions!

    1. How much phase and gain margin is acceptable for a power supply?

    Acceptable gain and phase margin values depend on the specific application.  First off let me state that higher margins typically sacrifice the response time of the control loop thus a design with high margins may not properly react to load changes resulting in unacceptable voltage droops.  A design with low margins may have very fast loop response yet potentially over-shoot the desired output voltage during load changes (often showing up as a high frequency ringing during step load changes).

    I discuss this and provide industry target values in the EDN article at the following web address:

    www.edn.com/.../Testing-a-power-supply---Stability--Part-three-

    2. How can I test the stability of an LDO that does not have external feedback components?  I recently encountered one that was unstable at low temperatures.  I seek a method to determine the control loop margin to predict this possibility.

    When you have no way to inject a signal into the control loop you can verify stability by providing a load step onto the output.  A load step from minimum to maximum expected load will result in either unacceptable ringing or unacceptable voltage droop if the loop is not properly compensated.  Generally speaking, if you observe more than 3 cycles of ringing on the output voltage before settling your margins are likely too low and you may risk instability. In this situation you must adjust the load impedance to increase the margin.  Many LDO datasheets will provide output capacitor limitations for just this reason.   If you follow guidelines on the datasheet you should realize good results.

    3. Can a step load response be used to determine stability?

    As described above, a load step can be used to determine stability.  By disturbing the output of a power supply one can determine the output impedance of the supply over frequency and use this to plot the phase and gain margins.  Companies do make such test equipment and they do have the advantage of not requiring you to open up the control loop for the measurement (adding a resistor in the feedback loop).  From what I have seen and read, it appears that these passive methods do not provide the accuracy of the traditional loop response measurement technique I describe in the EDN article and video. You want to inject and observe inside the control loop for the real picture.  By carefully adding the injection point resistor you can make stability measurements with your actual system load in place.

    Bob

  • Bob

    I am not sure what you mean here "From what I have seen and read, it appears that these passive methods do not provide the accuracy of the traditional loop response measurement technique". Are you referring to non-invasive impedance measurement? Not sure what other "passive" method you are referring to. But, using output impedance is MORE accurate that Bode plots which can give the wrong answer. Essentially output impedance is the same assessment as step load testing. Formulas exist to convert the step load 'Q' into phase margin and the answer is a specific phase number that is accurate.

  • Hi Charles,

    I haven’t used equipment that measures output impedance to determine stability, so can’t comment first hand on the relative accuracy.  A potential weakness with the technique is the need to decouple the power supply from the load.  Since a system load is almost always reactive it can have a significant effect on the loop stability, so changing the load changes phase and gain margins.  When simply bench testing a power supply, measuring impedance should provide accurate results, but for in-system measurements, especially where loads are very reactive, breaking the feedback loop and employing a Frequency Response Analyzer (FRA) may provide more accurate results.  We often suggest adding a small resistor in the feedback loop (25 – 50 ohm) with test points to make FRA testing easy after a system is in its final embodiment.  Setting the FRA injection level too high or too low can result in erroneous results, so must be adjusted carefully.  What has been your experience?  Thanks for the comment, Bob

  • hi Bob,

    I have a question in reference to the Video #3 "Measuring Noise". You refer to two kinds of noise in the output of a switching regulator, specifically, ripple noise & Transient Switch noise which is at high frequency.

    I use a Switching regulator to drive an LDO. When I measure the Transient Switching noise with a high bandwidth scope with a high quality probe, I am getting around 80mV pk-pk noise at around 250MHz.

    You mention that a decoupling capacitor can reduce this transient noise significantly. All decoupling capacitors are ineffective after 50MHz so how can it reduce the noise? At these frequencies which are beyond the Self resonant frequency, the capacitors will become inductive. So, I don't think they will remove this noise.

    What is your opinion about controlling this noise? Is this really something to be worried about in application ?

  • Hi George Thomas,

    Much high frequency transient noise is decoupled by inherent inductance of traces and connectors carrying the power.  I don’t agree that “ALL decoupling capacitors are ineffective after 50MHz”.  If placed immediately at the input to the load, a small MLCC can HELP attenuate high frequency conducted signals.  Many designers also employ a series ferrite bead inductor when powering sensitive circuitry.  You can find inductors specifically designed for this use.  An 80mV pk-pk signal at 250MHz for a few cycles would usually not concern me, unless it’s next to a 250MHz receiver or powering a 1V core with tight noise limits... so it very much depends on the application.  Emission caused by high frequency transients can be a bigger pain to deal with, and sometimes best handled by reducing them within the switching power circuit itself, but that’s a different discussion.  Thanks for the comment, Bob