Painting a picture for powering high-performance FPGAs


Paiting a power semiconductor

Last weekend when it was hot outside, I decided to do some touch-up painting around the house.  When the interior of the house was painted back in 1999, the painter dropped off a can of left over paint. 

Over the years, I have been using this paint to touch-up small scratches and little blemishes that won’t come off with soap and water.  A few hours after finishing the chore this time, I noticed that those touched-up patches were still noticeable.  I checked to see if the paint was completely dry, redid several patches with an improved feathering brush technique, and even pulled out the hair dryer to make sure the paint dried completely.  The patches were still noticeable!

The wheels in my head started turning, and I realized what happened over the years – a lot of time passed.  Who knows what happened to the paint on the walls or in the can.  Since I am a power guy, it reminded me of a similar power management issue one of my colleagues had a few months back. 

Larry (among others) was tasked to design the power management solution for a new high-performance FPGA.  He worked with point-of-load power management designs many years ago. Larry figured he could use an older, tried-and-true design that employed DC/DC converters familiar to him.  A 12V input to 1V & 5A output didn’t seem too difficult to implement.

After looking at the DC/DC converter specification and the FPGA’s voltage requirement, it didn’t take too long to figure out that the old, reliable point-of-load design wouldn’t work.

Back in the 90’s, processors used a 0.35 micron technology and required 3.3V or 2.5V input.  Nowadays, the latest and greatest FPGAs are made in sensitive, deep sub-micron, process technology and require a voltage of 1V or lower. Back then, internal voltage references weren’t that low! 

FPGAs also require tighter voltage accuracy and several other voltage rails that may require special power-up sequencing.  Fortunately, the newer point-load power solutions are still easy (maybe even easier!), and Larry's smart realization was to use a DC/DC converter released within the same decade as the FPGA.

Related Read:  Powering FPGA’s made easy

 FPGAs have come a long way over the years, and so has power management.   Have you been touching-up your FPGA power designs with old paint?

Click the links to view the latest point-of-load DC/DC converters, power modules, power management units, LDOs, and tested FPGA reference designs , and tell me about your FPGA power stories. 

Names have been changed to protect the innocent.

-Rich

Index of all Power House blogs. 

  • Very nice blog post. Good reminder for us to make sure that when we move to the next generation on the system technology, we should upgrade the power to the next generation too. Not doing so risks ending up with less-than-optimum solutions.