Mitigate overheating in ultrascale & ultrascale+ FPGAs

Accuracy and reliability are priorities for industrial and consumer embedded applications like motor control and high-precision medical equipment. In these types of systems, any failure could be fatal to the system and can cost a company millions of dollars. The most common point of failure is the power devices on the system, and the most common reason for failure is overheating, unmonitored power rails.

A conventional way to avoid these failures is to use a distant point-of-load solution, can be bulky and take significant board space. Plus, implementing a power monitor on each system power rail adds cost to the system. Hot spots in power ICs are generally near the power FETs through which the current flows. An easier and more cost-efficient way is to segregate the power FETs from the main power IC, which will create better heat dissipation and implement active supervision using power-good signals to monitor the power rails.

You can achieve the same level of reliability without paying a hefty price tag to buy multiple ICs by using an integrated PMIC like the TPS650860. The architecture of the device enables you to avoid overheating issues, along with monitoring each power rail to ensure system safety. The power-good signal implemented on each power rail saves your system from undervoltage lockout and overvoltage strike. You can program each power rail to monitor within a very tight tolerance.

Figure 1 shows the connection between the PMIC with the FPGA. Three buck controllers integrated into the device require external power FETs, which shift any hot spots out of the PMIC. Shifting the hot spot allows better heat dissipation in harsh environments when the FPGA is operating at full speed and ensures reliability of the PMIC.


Figure 1: Connection diagram

Along with translating the hot spot out of the PMIC, the controller architecture allows you to scale system size based on the power that the FPGAs need; you can select external FETs based on the current required on each power rail. You can design the system in such a way that each rail can deliver up to 10s of amplitude with a very high accuracy of +/- 3%. This in turn reduces system size and cost.

With all this flexibility you can power multiple FPGAs with this PMIC by just a simple OTP spin and optimize solution to mitigate thermal issues.

Additional resources