Low-dropout regulators (LDOs) are widely recognized for their low noise and high power-supply rejection ratio (PSRR). However, LDOs can also contribute to power efficiency when they are complemented with the right technique. You can design a low-noise and lean power supply by pairing low-quiescent-current LDOs with appropriate power-saving techniques such as dynamic voltage scaling (DVS) or power cycling. In this blog post, I’ll present some common power-savings techniques.
Mixed-signal processors such as microcontrollers (MCUs), MPUs and digital signal processors (DPSs) demand a high power supply during high-frequency processes, yet only require a fraction of that power during low-power modes or long sleep cycles. You can improve power dissipation by adjusting the voltage-supply levels accordingly to the demand. Let’s review a few popular DVS techniques and their respective technical resources.
Figure 1: Linear Regulator Power Solution Reference Design Block Diagram
The pink trace in Figure 2 shows the smooth transition from a 3.3V voltage supply to a 1.8V voltage supply; the green trace indicates the frequency change due to the MCU input-voltage change. From the test results in the reference design user’s guide, the quiescent current savings are 50% from 400µA to 200µA; in a battery-operating device, that represents months of battery-life extension.
Figure 2: MSP430 supply transition from 1.8V to 3.3V
Figure 3: Linear Regulator as a Dynamic Voltage Scaling Power Supply Reference Design Block Diagram
Figure 4: TPL0401A Resistance Versus LP3878 Output Voltage
Ultra-low sleep-mode current
Figure 5 is a block diagram of the Power Cycling Reference Design to Extend Battery Life Using an Ultra-Low IQ LDO and Nano Timer, which extends battery life by power cycling. Power cycling enables and disables the LDO or power stage to achieve great power savings by taking advantage of the low standby quiescent current of the LDO and nanotimer. The system activates periodically to analyze data, transmit data or execute commands. When the microprocessor completes the process, the system deactivates and enters an ultra-low IQ sleep cycle.
Figure 6 shows the substantial current differences. Over the lifetime of the battery, this savings could mean months or even years.
Figure 5: Power Cycling Reference Design to Extend Battery Life Using an Ultra-Low IQ LDO and Nano Timer Block Diagram
Figure 6: Comparison between Sleep Mode and Active Mode
LDOs are the number-one pick for low-noise, easy to implement small size power solutions. Thanks to their low quiescent current, they can also positively contribute to power efficiency when utilizing the right technique.
Jump-start your design with these TI Designs reference designs:
Read the part one and two of the “Drive MSP430 low-power even lower” Power House blog series.
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