With the increased interest in energy efficiency and energy conservation, a synchronous rectifier (SR) helps boost efficiency when converting offline AC power into 5V for USB smartphone battery charging. During this conversion, an SR controller integrated circuit (IC) needs proper biasing in order to provide the adequate drive to the SR MOSFET. The bias voltage is typically above 4V in USB applications. Because the BC1.2 USB battery-charging standard specifies a power adapter output in the range of 4.1V to 6V, you can bias SR controller ICs from that output, as shown in Figure 1.
Figure 1: Flyback converter with the SR controller biased from the output voltage
What if the output voltage drops below UVLO?
This biasing approach is simple, easy and has almost no additional cost. It works well when the output voltage is above 4V, but at <4V on VDD, the SR controller IC enters undervoltage lockout off (UVLO). The issue here is that the SR still needs to be operational when the output drops below 4V. In fact, it still needs to be operational before the output drops to 3V in USB smartphone applications. This is because battery-charging operations require constant-current operation, where an adapter keeps delivering constant current while its output voltage falls to help operations such as battery charging during dynamic power management (DPM).
Figure 2 illustrates typical 5V-3A power adapter output characteristics. Operation ceases when the output drops to 3V because at 3V, the lithium-ion battery cannot charge; thus, no bias power is necessary for the SR. As a matter of fact, a fault is actually identified when high current is present at ≤3V.
Figure 2: Typical 5V-3A power adapter output characteristics
When the output drops below 4V, the SR turns off, which causes undesired performance. First, the SR turn-off causes a constant current shift due to the voltage increase from the body-diode conduction, leading to unnecessary transients. Second, the current flowing through the SR MOSFET (QSR) channel now flows through its body diode. The resulting higher-power losses may cause a temperature rise that could cause thermal runaway and damage. Therefore, you need alternative approaches to keep the SR on before the output drops to 3V.
Biasing an SR controller using a charge pump
One alternative is to use a charge-pump circuit. Figure 3 explains the operation of a charge pump with the circuit. The VDD voltage on capacitor C2 is brought up to 2x Vp by switching S1 and S2 will alternate switching on/off, when the Vp pin is connected to the adapter output after the detected output voltage drops below 4V. As the output is between 3V and 4V, the SR bias voltage VDD is maintained at 6V to 8V, thus achieving the desired SR bias voltage.
This approach needs additional components and control functions to set up proper timing for S1 and S2. You can integrate these components and control functions inside an IC to simplify application designs, but you will still need three dedicated pins and a capacitor (C1) to fulfill the function.
Figure 3: Charge-pump biasing
Biasing an SR controller using a linear regulator
The SR MOSFET drain pin is applied with a pulse train during flyback converter operation. The pulse magnitude is well above 4V in USB smartphone power adapter designs. Figure 4 shows a linear regulator that can be used to regulate the linear regulator output to 5V which is connected to the SR controller VDD pin. But because you have to add four additional components, this approach becomes less attractive due to the increase of both cost and board space.
Figure 4: Pulse linear-regulator biasing
Biasing an SR controller using a simple regulator
As these first two approaches are generally not preferable in USB smartphone charging applications given their cost and complexity, newly developed SR controller ICs such as the UCC24636 accept a simpler bias approach using a “simple regulator,” as shown in Figure 5.
Figure 5: Simple regulation bias
The bias VDD pin accepts a wide voltage range from 4V to 30V – and the driver output is internally clamped to the MOSFET’s gate-voltage level, 10V. These features enable a simple regulator (placed externally with a diode and a resistor) to charge the VDD capacitor to a proper level across the input and load range. When the drain pin voltage is pulsing, the diode (D) rectifies the pulses, while the resistor (R) and capacitor (C) average out the pulses to deliver DC voltage and power to VDD.
Table 1 provides biasing results based on the TI Designs Universal AC Input to 5V/3A Output Reference Design, which employs the UCC28704 and UCC24636, a universal offline input, and a 5V-3A output flyback converter.
Table 1: Simple regulator biasing results
The results depict a minimum controller VDD voltage above 4.57V even if the converter output drops to 3V, thus maintaining plenty of bias voltage to keep the UCC24636 in operation.
When converting offline AC power into 5V for USB smartphone battery charging, an SR controller can help boost efficiency when biased properly.
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