Virtually all complex processors require some kind of power sequencing at power up and/or power down. The timing requirements vary depending on processor selection and the subsystems being powered. For example, the image processor in a multifunction printer (MFP) has several rails that need to power up and power down in a specific order to properly bias the internal circuitry and stagger the in-rush current at startup. In this post, I will review different ways to implement power sequencing and the benefits of using integrated load switches to do so.
Why use load switches for power sequencing?
Load switches provide design flexibility and simple control of subsystem power sequencing. Each rail can turn on and off independently without extensive processor intervention, and the rise and fall time of each rail is adjustable. This is possible because of features available in integrated load switches such as configurable rise time and quick output discharge (QOD). TI’s TPS22918 is an example of an integrated load switch that has both of these features available. Figure 1 shows examples of common subsystems.
Figure 1: General system block diagram of MFP subsystems
Using load switches over discrete metal-oxide semiconductor field-effect transistor (MOSFET) solutions also provides improved transient behavior and smaller solution size. You can read more about these benefits in the application report, “Integrated Load Switches Versus Discrete MOSFETs.”
If you need more protection throughout your design, you can place an eFuse at the input of any hot-pluggable loads to help against hot-plug transients and protect downstream DC/DC converters from an input voltage that is too high or too low. Unlike a discrete fuse, eFuses do not need replacing after a fault, resulting in reduced system downtime and decreased maintenance costs.
Power sequencing configuration options
Power sequencing requirements are unique to each processor and system configuration. Load switches control each power rail by adjusting the timing capacitance value on the CT pin and the resistance value on the QOD pin, without the need for external digital components such as oscillators, clocks or a processor. Figure 2 shows various configurations for implementing power sequencing in your system.
Figure 2: General-purpose input/output (GPIO) configuration
Figure 2 uses independent enables for each load switch to trigger power-up sequencing. Varying the resistance on the QOD pin achieves power-down sequencing.
Figure 3 uses one GPIO signal to enable all three load switches, but varies the capacitance at the CT pin to control power-up sequencing. Again, varying the resistance on the QOD pin achieves power-down sequencing.
Figure 4 routes the QOD output of the previous load switch to the enable pin of the next load switch. Adding an external resistor-capacitor (RC) in parallel to the QOD output achieves power-up sequencing. Once more, varying the resistance on the QOD pin achieves power-down sequencing.
Figure 4: QOD configuration
You can learn more about implementing power sequencing in your designs from TI’s Power Sequencing Reference Design Using Load Switches. Since timing constraints vary greatly between different applications and processor-to-processor communications, this reference design is not limited to one specific timing sequence. Instead, the design enables you to configure multiple timing configurations to fit system specifications.
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