"My advice is to get involved and get started,” — Jack Kilby
About 20 million reliability hours ago, we built our first gallium nitride (GaN) application board in TI’s Kilby Labs. We watched the oscilloscope in anticipation and were amazed at the textbook-like switching waveforms. Power GaN was at an early stage of technology maturity but showed tremendous promise. Integrating a driver and protection features would indeed make the perfect power switch. We knew there was lot of work ahead, so we took Jack Kilby’s advice.
Our early evaluation marked the start of a reliability journey, as we realized that traditional silicon qualification was not testing for hard switching. Many power-management applications hard-switch the field-effect transistor (FET), making this finding very relevant. Hard-switched circuits include buck and boost converters, power factor correction circuitry, inverters and motor drives. Hard-switching stresses the device in a different way, since it includes a brief moment where the device is subject to simultaneous high voltage and current as described in our white paper, “A comprehensive methodology to qualify the reliability of GaN products.”
We realized that the devices needed to be made robust to hard-switching. The methodology in use for silicon was not applicable to GaN, so we started hard-switching the FETs in a boost-converter test vehicle as part of our device development program. This issue of application robustness quickly became known in the industry, along with the need to collaborate, as described in our blog post, “Let’s GaN together, reliably.” These aspects catalyzed the formation of the Joint Electron Device Engineering Council (JEDEC) JC70 committee on wide bandgap power electronic conversion semiconductors, and have accelerated the availability of reliable GaN.
Reliability is our highest priority, and we knew that the release of a reliable technology to manufacturing encompasses much more than hard switching, as illustrated in Figure 1. The LMG341x family of devices has both reliable GaN and silicon, is manufacturable, incorporates protection features, is integrated into a low-inductance package, and is validated to work robustly in applications. These device features were achieved with coordinated efforts in device reliability, application robustness and manufacturability, in addition to considerable accelerated stress testing and failure analysis.
Figure 1: A methodical path to the manufacture of high-quality dependable products. In addition to substantial reliability effort in device engineering, application robustness and manufacturability programs, the LMG341x device also has design-for-reliability features and benefits from our participation on the JEDEC JC70 committee
We take successful designs through a standard qualification procedure, involving both GaN-only and LMG3410 devices. Nowhere is Thomas Edison’s quote, “Genius is 1% inspiration and 99% perspiration,” more true, and we have certainly made our devices perspire in hot and humid chambers. We have conducted over 20 million hours of reliability testing, as shown in Figure 2, broken down into four categories: manufacturing, application robustness, GaN device reliability and JEDEC qualification.
Figure 2: Pie chart showing the breakdown of the various categories of reliability testing hours
It’s easy to see how the reliability hours accumulate. GaN device reliability is designed through the understanding of the time-dependent breakdown failure mode, field plate engineering, the judicious choice of appropriate materials and thicknesses, and by engineering the epitaxially grown layers. We run large quantities of regular devices and special test structures specially designed for understanding failure mechanisms, testing 10,000 wafer-level structures and 8,000 packaged devices to build comprehensive reliability models and predict device lifetimes. Our model shows that the overall FET and high-field-withstand components have lifetimes of over 100 years.
We also tested devices for stable dynamic RDS(on) and hard-switching safe operating areas by routinely running them on application reliability test boards for 1,000 hours. Dynamic RDS(on) is a measure of the on-resistance that power-supply designers see during product operation and is a consequence of charge trapping by high fields. Dynamic RDS(on) reliability engineering consists of optimizing interfaces, developing in-process cleans that leave pure surfaces, depositing high-quality dielectrics and optimizing growth parameters of the GaN epitaxial layers. We test the multichip module (MCM) at the system level using our customer evaluation module card to ensure that there are no effects from the interactions of the components or in other modes of operation, such as synchronous rectification. We also test the MCM for extreme conditions like short circuits and lightning surges.
Manufacturability and use of the mature silicon infrastructure also forms a key part of our program. Silicon manufacturing processes are very cost-efficient, not only in wafer processing, but also in the packaging process of wafer thinning, die singulation and assembly. In order to develop good GaN manufacturing, we have run over 10,000 devices in burn-in boards, both for early failure detection and for longer-term high-temperature reverse-bias validation testing. We have also run the well-proven traditional (JEDEC) qualification on both the intrinsic technology and the product, including extending the major tests to 2,000 hours, double the regular stress time.
With 20 million hours of stress testing behind us, there are now many good reasons to find out more about the perfect power switch at http://www.ti.com/GaN.