Every year the Power Source Manufacturers Association (PSMA) and IEEE’s Power Electronics Society (PELS) work together to organize the Applied Power Electronics Conference (APEC), the largest and most influential power electronics conference in the world. APEC 2015 in Charlotte, North Carolina, marked the conference’s 30th anniversary.
PSMA and 3-D packaging
PSMA presented a new roadmap and 3-D packaging report. This represents a big change for PSMA, which has been a sleeper organization for the last decade. This year, a few outstanding members spent extra time to create a 335-page report on 3-D power-packaging technology. I believe one key PSMA member, Louis Burgyan of LTEC Corp., put a few months of his life into this report. The report is available free to PSMA members and seems to have details that the typical PSMA roadmap reports have not previously covered. One of the 3-D packaging technologies mentioned that is used by several silicon manufacturers and even one gallium nitride (GaN) field-effect transistor (FET) supplier is a method of embedding silicon inside an FR4 PC board.
I found three suppliers using this packaging method: Infineon's DrBLADE, GaN Systems’ GS665XX GaN FETs and TI’s LMZ21701 1A nano module. The method provides low inductance and a lower-cost package than other 3-D package methods. The lower parasitic inductances allow faster switching-edge times that result in better efficiency.
The process begins by placing many silicon die or GaN die inside an FR4 PC board when it is formed, using conventional printed circuit board (PCB) methods. A laser removes the PCB material above the die, where contacts need to be made to the silicon regulator, FETs or GaN die. Copper plating fills in the laser holes, which now connect up to the next copper layer added to the board. Extra components can be added on top of the PC board for 3-D integration. Finally, the PC boards are cut up into many millimeter-size PC boards and become a package that can be mounted on the system board. Figures 1 and 2 illustrate two examples of the final products.
Figure 1: A side-view example from the PSMA report of a PC board with a FET inside
Figure 2: A side view of the TI LMZ21701 with a switcher die inside the PCB and an inductor added on top
GaN industry gaining acceptance
Another trend continuing at APEC this year was more activity about wide bandgap material – meaning that GaN FETs are still being talked about. Eric Persson of IR/Infineon mentioned during the S17 professional seminar that they had made a 99% efficient proof-of-concept 2.5kW power factor correction (PFC). This was also on display in their booth. The PFC used two GaN FETs and two super-junction FETs in a totem-pole full bridge. I saw the same configuration and almost the same board layout at Panasonic on the exhibit floor, but the latter was slightly different. I believe Panasonic used four of their enhancement-mode gate-injection GaN FETs in it and no super-junction FETs.
Panasonic had a new quad-flat no-lead (QFN) package for its 600V 10A/15A gate-injection transistor (GIT) GaN FETs, I assume to match the pinout of Infineon’s super-junction FET packages. Even though the Panasonic FET had a +1.2V enhancement-mode threshold, that is not really enough to keep the GaN FET off when switching, so the gate must still be brought to -3V.
Longtime GaN player EPC showed a 500W 1/8 brick converting 48V to 12V. It did require 400 cubic feet per minute (CFM) of air, but I think that’s normal for that market.
Tuesday night was the GaN/silicon carbide (SiC) rap session, using the largest room ever for a rap session at APEC, with only standing room in the back. Although I thought it was not lively enough for a traditional rap session, a couple of important viewpoints are worth repeating:
- Whether or not GaN helps efficiency that much is still hotly debated, at least the way people are using it today. Only tenths of a percentage improvement in efficiency.
- They are not enough controllers or drivers out there in the market to make it easy to use GaN.
- The biggest point made was that GaN will not take off just because the total system cost might be lower. The GaN FET component itself must cost the same or less than silicon FETs to take off in the market.
Hope this gives you a little taste of APEC 2015 this year.
For more information about what TI showed at APEC 2015, visit: www.ti.com/apec2015