We’ve all done it, left our phone charger at home or at our desk, but the phone itself is in our pocket or in our hand. No big deal, right? Actually, it is a big deal. The power consumed by an unused charger that is basically doing nothing is considerable when you realize there are millions of these, eating up an estimated 10% of domestic power consumption.
One surefire way to reduce consumption is to unplug the charger when it isn't actively engaged with the device. Old habits are hard to break. So instead of trying to convince the consumer to pull that plug, the goal is for us, as power-supply designers, to design a charger, or adapter, that consumes as little power as possible in an unloaded state (also known as no load or standby).
So how low can you go without pulling the plug? Leading handset manufacturers recently set up a score chart rating system, in which stars are awarded based upon no-load power consumption, to encourage adapters to be designed for minimal standby power (Figure 1). Although there are demands for five star ratings, the ultimate goal is to drive the target rating down to a “zero-power” solution. An adapter is considered zero-power if its no-load power is measured to be less than 5mW when measured with an input voltage of 230Vac. Achieving less than 5mW of no-load power isn’t an easy task, as it involves compromises with other design targets.
Figure 1: Handset manufacturers developed a score chart to help consumers choose the most efficient handset charger based on no-load power consumption
Texas Instruments recently released a chipset: the UCC28730 zero-power primary-side regulation (PSR) flyback controller and wake-up monitoring and the UCC24650 200V wake-up monitor for fast transient PSR. This chipset provides a wide range of features that enable a <5mW standby power design without compromising design targets such as fast transient response, low component count and small size. Figure 2 shows a typical application of the UCC28730/UCC24650 chipset.
Figure 2: Typical flyback converter application using the UCC28730/UCC24650
A high-voltage startup switch eliminates the constant loss associated with a startup resistor. PSR reduces component count and the associated biasing losses for an opto-coupler and voltage regulator. The undervoltage lockout (UVLO) hysteresis of the UCC28730 allows the VDD voltage to drop as low as ~8V during standby without triggering UVLO. Using a low bias voltage of (for example) 12V at no-load combined with the low wait-state supply current (typically 52µA) will only “cost” approximately 0.624mW. The UCC24650 also has very low bias current (typically 41µA) and is biased directly from the output rail, resulting in approximately 0.205mW of power consumed in a 5V adapter. Total bias power uses less than 0.830mW of the total power-consumption budget.
Unavoidable losses that need to be accounted for would be the secondary-side leakage losses, associated with the output capacitor and the Schottky diode. A typical 10W design could result in leakage losses comparable to the bias power. The combined biasing power and these leakage losses constitute the minimum amount of energy needed to be delivered each switching cycle.
The act of delivering this energy creates losses proportional to the energy expended each switching cycle. The best overall way to reduce standby power is to reduce the switching frequency and to minimize the peak current during no-load conditions. The wide dynamic range of the UCC28730’s control law reduces the peak current to one-third its full-load value and allows the switching frequency to drop as low as 32 Hz at no-load, keeping dynamic switching losses low while sustaining standby operation.
With no-load power consumption minimized, the remaining design targets need to be considered. The low switching frequency would normally require large output capacitance to maintain output voltage regulation during large load transients. The UCC24650 is designed to send a wake-up signal to the UCC28730 so it can rapidly respond to load changes, minimizing output voltage droop without needing a large output capacitor.
The UCC28730/UCC24650 chipset can help achieve zero-power status by minimizing its own contribution to standby power, yet still operate in a way to minimize system-level losses. Together, the UCC28730 and UCC24650 require less than 1mW to remain active during standby, but are still ready to respond to sudden heavy load steps. The wide dynamic control range of the UCC28730 reduces the switching frequency and peak current during standby. With no external components required and minimal bias power, the UCC24650 wake-up monitor complements the primary-side UCC28730 to meet both no-load power and transient response. You still must pay strict attention to every possible contributor to ensure minimal collective standby losses, but achieving a five-star score or even zero power is achievable with the UCC28730 and UCC24650.
Here are a few reference designs using the chip-set that will help you on your way to Zero-power!