How to reduce total harmonic distortion to below 10%

A common concern in LED lighting has been keeping THD (Total Harmonic Distortion) below 10%. Power sources act as non-linear loads and draw a distorted waveform that contains harmonics. These harmonics can cause interference in the working of other electronic systems. Therefore it’s important to measure the total effect of such harmonics. Total Harmonic Distortion gives us the information about the harmonic content in a signal w.r.t. fundamental component. Higher THD means higher distortion present on the input mains or lower power quality.

This requirement led me to test a design approach using a 15 W down-lighter (isolated) design based on TPS92314 configured for seven LEDs in series with 3.1 V forward voltage and 0.7 A rated current running from 150 – 265-V AC input. I followed below points to achieve a THD of 8.7 % at 240-V ac.

Before we get into actual implementation, here are two important equations from this application note that are needed to complete this test. 

In this case, k comes out to be 1.68 and we plot THD vs “m” below for k = 1.68 with the help of above equations. 

We also notice from the below figure that with increase in k (at a particular “m”, with m<k), THD increases. 

Thus, going back to definitions of “m” and “k”, we notice that by increasing turns ratio (n = Np/Ns) and increasing the delay time of the converter, we lower the THD. Besides these parameters, the EMI filter design also plays an important role in THD improvement. The three design considerations to lower the Total Harmonic Distortion:

1. Increasing transformer turns ratio (n = Np/Ns) increases the reflected voltage. This means higher voltage stress on the switching FET and higher cost. In this particular case, we kept the reflected voltage at around 174 V by keeping the turns ratio near 10. FET rating must be higher than sum of Overshoot voltage, (LED maximum voltage + Output Diode voltage drop) * Turns Ratio and peak AC input voltage. It turns out to be nearly 640 V [= 50 V + (20 + 0.5) * 10 + 1.414 * 265]. I used a 700-V rated FET with low drain to source capacitance of ~16pF.
2. Increasing delay time of the converter leads to lowering of THD. I changed the resistor from calculated 5.6k to 6.2k. Delay time depends upon the primary inductance of the transformer and drain to source capacitance of the FET. Delay time comes out to be around 280ns.
3. Adding EMI filter at the input.In this example, common mode choke of 80mH with a capacitor of 68nF, 275V ac was added at the input along with a π filter comprising of 1mH drum inductor and two capacitors of 33nF, 400 V each following the bridge. This helps us realize the corner frequency of the differential filter to be at 2.15 kHz. Icalculated these values in multiple iterations after looking at the conducted EMI curve with the help of Line Impedance Stabilization network and Spectrum Analyzer. Initially, without any line filter, we saw a peak of around 85dBuV at 100 kHz (Fsw of the converter). The spectrum was exceeding the CISPR 15 Class B standard limits all the way till 1MHz after which the spectrum was under the limits. An EMI filter was absolutely required. I increased the common mode choke value in steps, and saw its effect on THD performance (Increasing capacitor above a certain points will have degraded PF performance). Ultimately, it came to around 80mH and 68nF, with a cut off frequency of 2.15 kHz with an attenuation of more than 30dB leading to ~55.78dBuV at 100 kHz.  Resulting spectrum shifted down and it helped the light meet CISPR 15 standard as well (both quasi-peak and average limits). The THD improved to ~9-10% as a result of this change. Leakage inductance associated with the common mode choke helped realize a differential filter.