Input bypass capacitors and output capacitors play vastly different roles in all buck converters - whether synchronous or not. But it is in high-current, multi-phase applications where making an incorrect assumption of similar roles can seriously affect the design performance. Many designers make a serious effort to keep both groups of capacitors as close as possible to the main power switches or integrated converter.
For a good source on general layout considerations for converters see Constructing Your Power Supply - Layout Considerations by Robert Kollman.
In buck converters the highest and fastest switching currents occur in a loop consisting of the input capacitor, high side buck FET and low side diode or synchronous rectifier. It is critical that all these 3 elements create the shortest loop to minimize high frequency (50-200 MHz) radiated noise and peak voltages on the switching elements. In multi-phase applications it is essential that for each phase that both switching elements and the input bypass capacitors create the smallest loop feasible. However, the power stages themselves can be spread out somewhat for thermal purposes as long as each stage keeps its input capacitors close by.
Any distance of the input capacitors from the power stage will result in substantial radiated emissions and added voltage stress on the switches themselves when currents are switched at several Amperes per nanosecond.
On the other hand, the currents from the power stages are smoothed out significantly by the output inductors such that the max change of current vs. time is generally less than 1/100th that in the input capacitor. This represents more than a 40 dB reduction in peak field strength for a given current loop. Major purpose of the output capacitors is to reduce ripple seen at the load interface, and to present to the load low source impedance in the case of load transients. Stray inductance between the power stage and output capacitors does not defeat this function. Any stray inductance in the path between the power stage and the output capacitor just gets added to the inductance of the main output inductor. Only if the path inductance is a significant percentage of the main inductance will any measureable effect be seen in the balancing of currents between the phases. Hence, closeness of output capacitors to the power stage is not critical.
What is critical with the output capacitors is for them to achieve ripple cancellation between the phases to reduce peak to peak ripple. These capacitors need to be next to each other and in one area to achieve this. Early multi phase layouts (mine and others) had the output capacitors for each phase close to the power stage. When measuring ripple at these output capacitors I found it to be much higher than expected, and to be at the switching frequency of each of the phases, not at the expected switching frequency times the number of phases. This is because the inductance of the paths between the phases forces the ripple currents of each phase to go mostly to the capacitors closest to that phase.
In the early design I did, I had capacitor banks on each phase with 3 milli-ohms impedance at 300 kHz, the switching frequency. With good design practices a one inch path between phases can be reduced to about 1 nH. At 300 kHz that 1 nH is 2 milli-ohms impedance, thereby upsetting the presumed cancellation of the switching frequency fundamental at the output. For designs with more than two phases in which harmonics of the 300 kHz switching frequency contained in the inductor current saw tooth are also presumed to be cancelled, the added inductive impedance is even worse. For example, with 4 phases, each at 300 kHz, all harmonics below 1200 kHz need to be cancelled.
On the other hand, with the output capacitors all in one area, the added path inductance gets added to that of the main inductor of each phase. However, this inductance of 1 to 5 nH is much less than the value of these main inductors, and even well below the tolerance of these inductors. Hence, the path length imbalance will have significantly less effect than the imbalance due to inductance tolerance.
A good example of a layout with capacitors all close together is the 6-phase PMBus power reference design, PMP9738. Output capacitors are on both top and bottom side of board to keep them close. From the dynamic step load response waveforms on page 2 of the Test Report, switching frequency ripple is well under 10 mV peak to peak, even at 250A load.
Below is the output ripple from a previous 6 phase design with same controller and power stages, with each phase having its own capacitors. Each phase is operated at 600 kHz. Ripple is at this same frequency and over 20 mV p-p.
Now PMP9738 with same 6 phases on, with each phase at the lower 300 kHz for better efficiency: Ripple is now much lower at less than 7mV p-p. However, cancellation is not perfect here even with all capacitors close together. In practice, when output ripple is below 10 mV p-p, increasing number of phases above 3 does not further reduce ripple as the output with only 3 to 5 phases enabled showed similar ripple.
Keeping the output capacitors close together allows for significant output ripple reduction, even when a lower switching frequency is used for efficiency purposes.
Additional Resources:
- Download the TI Design “High-Density, 200-A (255-A Peak), 6-Phase DC/DC Buck Converter with PMBus Interface Reference Design” and PMP10393 for <900mV output applications off 12Vin
- NexFET solutions (high-efficiency power MOSFETs)
- TPS53661: For a detailed datasheet and other design support tools, please contact VR@list.ti.com: Part can be used in both Intel and non Intel applications. Specify whether for Intel or non Intel application. If for Intel application, a current CNDA with Intel Corporation is required. First major application of PMP9738 was for a non Intel design.
