Reducing high-speed signal chain power supply issues

Other Parts Discussed in Post: TPS7A8300

Have you ever come across a lack of performance in the signal chain only to realize the issue was originating in the power supply?  In this blog, I will describe some of the issues encountered in the signal chain due to the power supply and how to resolve them.

A high-speed signal-chain design can have the following two elements: 1) a receive path with amplifiers and an ADC or 2) a transmit path with a DAC followed by an amplifier.  The following focuses on the power supply interaction with the signal chain and how to achieve the best performance possible.

Starting with a DC/DC converter noise spectrum, we see that the supply noise sources are the same as those present in the signal chain:

Thermal noise:

  • 1/f from DC to ~1kHz
  • Flat-band noise to 30kHz
  • Thermal noise is then rolled off by the limited bandwidth of the error amplifier

Switching noise present at the DC/DC converter switching frequency and harmonics.


The noise has two main components, the thermal noise and the switching noise.  Each component may have a different impact on the end application, thus eliminating one vs. another may be more critical in your application.

If the end application is using an averaging technique in the signal chain, then your system may not be too sensitive to the thermal noise, but the switching noise will create ghost signals.  If your system resolution is low, (8bit to 10bit), neither the thermal noise nor the switching noise will strongly affect your system performance, and a DC/DC converter may be as sufficient as a power supply.  If you are transmitting data at a high speed requiring a high dynamic range, your system will require much better performance than that of the DC/DC converter. In this case, a linear voltage regulator will need to be inserted after the DC/DC converter to reduce both thermal and ripple noises.

This is where low dropout regulators (LDOs) enter the picture.  For optimum power efficiency, the design needs the dropout to be less than 100mV at your specified current.  Note that an LDO’s pass element (and other packaging parasitic) creates a voltage drop that is linearly related to the output current.  This implies that a 1V dropout (not a low dropout LDO) at 1A would only have a 100mV dropout at 100mA.  In this example, the pass element would have a 1Ω slope.

Modern low dropout voltage regulators have dropout specified below 200mV at their max load.  For example, the TPS7A8300 has a max 200mV (under any input voltage, temperature and other operating conditions) at 2A.  If a bias voltage (not required for supply voltage above 1.4V) is used, the maximum dropout then becomes 125mV (see Table 1).  When setting the voltage drop across the regulator for nominal operation, you need to consider input supply tolerance, output supply tolerance and AC performance such as PSRR.  The larger the voltage drop, the better the PSRR performance will be.  Note that high voltage drop is also synonymous with higher power dissipation.

Table 1: TPS7A8300 dropout specifications

Any LDO thermal dissipation can be approximated with:

Note that the ground current does not show up here. It is understood that it will always be orders of magnitude smaller than the load current.  This simplification is not true for light load, so bear that in mind when using this formula.

The efficiency then becomes:

With dropout voltage such as those shown by the TPS7A8300, it is possible to operate at a 250mV voltage drop across the LDO, meaning that for a 1.25V output voltage, the efficiency is 83.34%.  As the output voltage is increased, the efficiency increases as well. When using a 1.8V output voltage, keeping the same voltage drop across the LDO increases the efficiency to 87.8%.

By using an LDO after the DC/DC converter for the signal chain power supply, the system will exhibit lower noise, either thermal or switching. A low noise LDO (6µVRMS TPS7A8300) with excellent PSRR (60dB at 1MHz) is shown driving the high-speed DAC DAC38J84 (figure 2) with results compared to the DC/DC converter whose voltage ripple are being attenuated by a dual π-filter.


Figure 2: TPS7A8300 vs π-filter

Using an LDO, rather than a π-filter, results in a smaller PCB layout while enabling higher performance in the signal chain.  The power dissipation cost to the system is minimal versus the LDO as the π-filter also has a parasitic resistance.

When a system does not perform as expected and the solution cannot be found in the signal path, making an analysis of the power path may result in signal chain performance limitations.  The use of a high performance LDO, either as an upgrade of the existing LDO or as an additional stage to power the signal path can improve the system performance without any major upgrade to the signal path.  Keep tuned to the Power House blog for more articles.

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