5 converter topologies for integrating solar energy and energy storage systems

Other Parts Discussed in Post: TIDA-01606, TIDA-010210

With energy storage systems prices becoming more affordable and electricity prices going up, the demand for renewable energy sources is increasing. Many residences now use a combined solar energy generation and battery energy storage system to make energy available when solar power is not sufficient to support demand. Figure 1 illustrates a residential use case and Figure 2 shows how a typical solar inverter system can be integrated with an energy storage system.

Figure 1: A residential solar energy generation and energy storage system installation

Figure 2: A typical solar inverter system with an energy storage system

In the best-case scenario, this type of system has highly efficient power management components for AC/DC and DC/DC conversion and high power density (with the smallest possible solution size) that are highly reliable (with the lowest losses) and enable fast time to market. Those requirements are not always achievable at the same time, however, and you will need to make trade-offs on the best power-conversion topologies for these subblocks.

What existing power topologies for AC/DC and DC/DC buck and boost power converters have in common are half bridges or converter branches that run interleaved, either to increase power levels in a DC/DC converter or to achieve three-phase operation in an AC/DC inverter or power factor correction stage by placing three branches running in 120-degree phase shifts. Figure 3 shows simplified schematics of five power topologies.

Figure 3: Power topologies for half-bridge and branch equivalent

  • Topology No. 1: In the two-level converter topology, pulse-width modulation (PWM) signals are applied complementary (with a dead-time delay to avoid shoot-through because of overlapping switching signals) to power devices Q1 and Q2. For the positive sine wave at the output, the duty cycle applied is >50% at Q1. For the negative sine wave at the output, Q2 has a >50% duty cycle. It is a simple concept to control the output power, but output signals before the line filter have a full bus voltage swing, which requires a larger filter to reduce electromagnetic interference. The ripple frequency into the filter is the PWM frequency, which affects the size of the filter.

Three-level topologies allow the use of smaller passive components and have lower EMI compared to two-level converters. There are four three-level topologies:

  • Topology No. 2: The T-type topology is named for the way that the transistors are arranged around the neutral point (VN). Q1 and Q2 connect between the DC link, and Q3 and Q4 are in series with VN. The ripple frequency seen by the filter is equal to the PWM frequency applied to switches Q1 through Q4. This defines the size of the filter components to achieve the required low total harmonic distortion at the AC line frequency. Q1 and Q2 see the full bus voltage and need to be rated at 1,200 V for an 800-V DC-link voltage in the system. Since Q3 and Q4 connect to VN, they see only half the bus voltage and can be rated at 600 V in an 800-V DC-link voltage system, which saves costs on this converter type. See the 10-kW, Bidirectional Three-Phase Three-Level (T-Type) Inverter and PFC Reference Design.
  • Topology No. 3: In the active neutral point clamped (ANPC) converter topology, VN connects with active switches Q5 and Q6 and sets VN in the middle between the DC-link voltage. Like the T-type converter, the ripple frequency seen by the filter is equal to the PWM frequency defining the size of the AC line filter. What’s nice about this architecture is that all switches can be rated at half the maximum DC-link voltage; in an 800-V system, you can use 600-V rated switches, which positively impacts cost. When turning off this converter, it’s important to limit all voltages across each switch to half the DC-link voltage. In other words, the control microcontroller (MCU) needs to handle the shutdown sequencing. TI’s TMS320F280049C and other devices in the C2000Tm product family have configurable logic that allows the realization of shutdown logic in hardware to offload software tasks for the MCU. See the 11-kW, Bidirectional, Three-Phase ANPC Based on GaN Reference Design.
  • Topology No. 4: The neutral point clamped (NPC) converter topology is derived from the ANPC topology. Here, VN connects through diodes D5 and D6 and sets VN in the middle between the DC-link voltage. The output ripple frequency seen by the filter is equal to the PWM frequency defining the size of the AC line filter. Like the ANPC topology, all switches can be rated at half the maximum DC-link voltage, but instead of two more switches, there are two fast diodes. The NPC topology’s slightly lower cost compared to the ANPC topology comes at the expense of slightly lower efficiency. The requirements for shutdown sequencing are also identical to the ANPC topology. It is easy to derive an NPC topology from the ANPC reference design mentioned above.
  • Topology No. 5: The flying capacitor topology already tells you what’s happening in this converter; a capacitor connects to the switch nodes of the stacked half bridges realized by Q1 and Q2 and Q3 and Q4. The voltage across the capacitor is limited to half the DC-link voltage and shifts periodically between V+/V–; power transfers when shifted. This topology uses all switches during the positive and negative sine wave. In this topology, the output ripple frequency seen by the filter is twice the PWM frequency given each cycle shift of the flying capacitor, resulting in a smaller-sized AC line filter. Again, all switches can be rated at half the maximum DC-link voltage, which positively impacts cost.

Table 1 lists the benefits and challenges of the different topologies.


TIDA-01606 in 2L

T-Type 3L





derived from ANPC


Flying capacitor 3L

  • Simple control scheme
  • 2 switches only
  • 2 PWM
  • Easy control scheme
  • Q3/Q4 see 1/2 VDC
  • Better EMI than 2L
  • fRIPPLE = fPWM
  • Good efficiency
  • All switches see 1/2 VDC
  • Better EMI than 2L
  • Lower cost than ANPC
  • All switches see 1/2 VDC
  • Better EMI than 2L
  • fRIPPLE = fPWM
  • 4 PWM
  • Highest efficiency
  • Only 4 HF FETs (& 1Cap)
  • fRIPPLE = 2 x fPWM
  • Smallest magnetics
  • Lowest EMI
  • Q1/Q2 see full VDC 
  • High EMI for bigger fPWM 
  • Passives are biggest 
  • Q1/Q2 see full VDC 
  • 4 PWM
  • More complex control scheme
  • Shutdown sequencing critical
  • 6 PWM
  • Lower efficiency than ANPC
  • More complex control
  • Shutdown sequencing critical
  • Initial charging of flying capacitor
  • Shutdown sequencing critical

Table 1: The benefits and challenges of different converter topologies

All four three-level topologies have clear advantages on power density (with the smallest possible solution size), highly reliable operation, and fast time to market over traditional two-level converters. Using wide band-gap devices and high-performance MCUs increase these advantages even further, at a comparable cost.

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