Someone once told me that less than half of the components actually appear in the schematic of a buck converter. The rest of the components are (unwanted) bonus, resulting from the board layout design and the parasitic elements associated with the components selected.
EMI and output noise depend on all of the components – those in the schematic as well as the bonus ones. In my experience, we need to be especially careful with the bonus components in the high di/dt loop. They can cause misbehavior and higher stress in the converter and also result in higher output noise and EMI. The size of the high di/dt loop in the PCB layout has to be kept to a minimum to minimize the high di/dt loop inductance and the ringing on the SW node. High dv/dt nodes, like the SW node, should be kept as small as possible to avoid capacitive coupling to other nodes, but must be large enough to handle the required current. Watch a video on best practices for EMI and board layout and go inside TI's three meter chamber to test the evaluation board.
When it comes to IC selection, the pin-out of the IC is often overlooked. But when it is time for a board layout design and EMI tests, the pin-out of the IC can be quite a critical piece in the overall design and performance.
In my opinion, high performance board layout of a switcher can be made easier with thoughtful pin assignment of the switcher IC.
A good pin-out should enable the engineer to implement the following guidelines:
- Minimize the critical, high di/dt loop.
- Keep the high dv/dt nodes as small as possible, on as few layers as possible.
- Protect the sensitive, noise susceptible nodes in the circuit.
Here is an example, using the new LM43603 and LM46002 SIMPLE SWITCHER Synchronous converters:
Having the VIN and PGND pins right next to each other enables the engineer to place the input capacitor right next to the IC and effectively reduce the high di/dt loop area to a minimum. Smaller loop area means lower inductance. Lower inductance in the high di/dt loop will produce less ringing on the switch node, which will then result in less noise coupling to the output through the parasitic capacitance across the inductor. Overall, the minimized high di/dt loop area results in lower EMI and quieter output voltage.
Placing the SW pin on the opposite corner of the IC (with respect to VIN and PGND) allows the engineer to connect the inductor directly to the pin with a short and wide trace. This enables the board designer to avoid running the high dv/dt SW node to other layers. It minimizes the capacitive coupling of the fast SW node to other nodes that are susceptible to EMI and noise.
Speaking of nodes that do not like noise, the feedback pin is thoughtfully placed on the opposite (far) corner with respect to the SW node. Keeping the feedback node away from noise sources is important for the normal operation of the buck converter. Also, having the AGND pin right next to FB allows the engineer to place the resistor divider right next to the FB pin, making the sensitive node as small as possible.
Below is a complete layout of the LM43603 and LM46002 SIMPLE SWITCHER synchronous buck converters. The layout example implements the guidelines mentioned above, resulting in a design with excellent EMI performance. For more information on the topic, read the application report “Low radiated EMI layout made simple with LM4360x and LM4600x.”
