Understanding and managing buck regulator output ripple

Dan Tooth co-authored this technical article

Your new design needs to fit twice as much into half the space and cost nothing – sound familiar? You selected the smallest point-of-load regulator and generated the tightest layout you could with the most cost-effective passive components. So far so good. But then you look at the output ripple on your critical rails and it’s not what you expected. What’s going on?

Let’s start by understanding what makes up the output ripple on a buck DC/DC regulator. It is a composite waveform. Traditionally only the three dominant elements shown in Figure 1 have been considered:

  • A triangular wave generated by applying the inductor current ramp across the equivalent series resistance (ESR) of the output capacitors. A 22-µF X5R ceramic capacitor may have an ESR of only 2 mΩ. Considering an inductor peak-to-peak current ripple of 1 A, the ESR ripple is 2 mV (less if you’re using multiple parallel capacitors).
  • A pseudo-sinusoidal component due to output capacitance. For the same output capacitor and ripple current as in the bullet point above, the capacitive ripple will be around 8 mV (less for multiple parallel output capacitors).
  • A square component generated across the output capacitor equivalent series inductance (ESL). For a 22-µF X5R capacitor, the ESL is around 0.5 nH, which generates a ripple of about 2 mV.

Figure 1: Typical output ripple waveforms

However, what you measure has spikes on the edges and a higher square-wave content that changes polarity when you reverse the inductor shown in Figure 2:

Figure 2: Measured output ripple

What has caused these undesirable components? And more importantly, what can you do about it?


When you selected your inductor, the self-resonant frequency (SRF) was above your regulator switching frequency, so all was good. Let’s re-look at that – the inductor has an SRF because it has a parallel parasitic capacitance. Applying the fast edge of the switching voltage to the parasitic capacitance generates a large current spike through the capacitor, which in turn generates a large voltage spike across the ESL of the output capacitor (see Equation 1):


To reduce this spike:

  • Select an inductor with a smaller parasitic capacitance. Look for the highest SRF value for the inductance and rating you need. Lower inductances tend to have lower parasitic capacitance (as do lower current ratings), so don’t over-specify the inductance or current rating.
  • Reduce the output capacitance ESL. Choose the smallest capacitor package size that meets your output capacitance requirements. Using multiple smaller capacitors in parallel means the package size (and hence the ESL) of each capacitor can be smaller, while having inductors in parallel will also reduce the total ESL.
  • Reduce the transient voltages (dV/dt) of the switch node (increase the value of t). Some regulators may allow direct control of the switch-node edge, but more often you may be able to place a small resistor in series with the bootstrap capacitor to slow the edge. This can impact efficiency, so the first two options are preferable.

Square wave

Let’s say that you selected a cost-effective, unshielded inductor. The magnetic field from an unshielded (or resin-shielded inductor) can spread beyond the physical body of the component. The simulation plots in Figure 3 show the field for an unshielded open drum inductor and a fully shielded molded inductor. 

Figure 3: Magnetic field for unshielded drum and shielded molded inductors (Source: Courtesy of Coilcraft)

This compact layout has output capacitors sitting right next to the inductor. The escaping magnetic field couples to the ESL of the capacitors (and to a lesser extent the output track loops) and generates the square-wave component. When the inductor is reversed, the current in the inductor and the magnetic field is reversed (like swapping the dot in a coupled inductor), so the square-wave component is inverted.
To reduce this effect:

·       Select a shielded inductor to reduce the leakage flux that generates this coupling. If you’re using unshielded or semi-shielded inductors, selecting an inductor that is larger in the x-y dimension but has a lower profile will reduce the airgap height and hence the fringing flux.

·       Reduce the output capacitance ESL as described above.

·       Don’t position the output capacitors and tracking directly next to the inductor, where the field is highest. Where space is critical, consider placing the inductor on the opposite side of the board to the rest of the regulator circuit in a clamshell construction. This moves the output capacitors away from the plane of the inductor where the magnetic field is strongest.

Now you can look at your output ripple waveform and unpack the different components. By choosing the right external passives and making some careful decisions on layout, you can still achieve a tiny, cost-effective solution and optimize the output ripple for your application.
Additional resources

·       Read the Analog Design Journal article, “Select inductors for buck converters to get optimum efficiency and reliability.

·       Download the application reports, “Output Ripple Voltage for Buck Switching Regulator” and Space Optimized, ‘Clam-Shell’ Layout for Step-Down DC/DC Converters.

  • Hi Sway

    Have a look at this white paper (pages 3-4) which explains this in more detail:  https://www.ti.com/lit/ml/slup407/slup407.pdf

    The inductor is rotated by 180 degrees - see below:



  • Hi Jim,

    Have a nice day. I don't understand the spinning 180deg and resoldering mean. Would you please give me some pictures of the layout guide? let me know clearly.

    Thanks a lot, looking forward to your reply


  • The inductor current during start up will depend on a number of factors which can be slightly different between different devices, control schemes etc.  In steady state the duty cycle is set by the Vin/Vout ratio.  However, when the load current is increasing (at start up or when there is a transient load) the duty cycle increases. 

    For a load transient where Vout is already in regulation, in the most basic case the HS FET turns on 100% of the time, the current ramps in the inductor until the new steady state is reached.  In many case the regulator has a maximum duty cycle or minimum off-time and this means the current increases in a number of steps. 

    At start up, the output voltage is below the required level, and current is soured to charge up the output capacitors.  Again in the simplest case, the HS FET is turned on and the current ramps in the inductor, and continues to ramps until the output capacitors are charged and the voltage has reached the required level.  The current could reach and be limited by the maximum current limit in the device and could pull a large inrush current from then input supply.  However many devices have a soft start feature that means the current limit is reduced during start-up and/or when the output voltage is below the required level.

    You mention a small inductor - a lower value of inductance will allow the current to ramp up (and down) faster.  Operating in DCM is not in itself and issue.  The DCM threshold is at low current so the peak inductor current won't be an issue.  The highest peak current in the inductor is at full load and during transient load steps and during start up.  Again the regulator current limit should protect the MOSFET.


  • Hi Jim, 

    Regarding buck, most discussion is based on the stable state.

    I am not clear about the  indunctor current wave during the startup and power off stage.

    Could you demostrate the indunctor current wave during the startup and power off stage and i wonder if there is any chance to reach the peak current during the startup stage due to the charge of Cout?

    Besides,   selecting a small inductor would increase the r and is there any chance to enter the DCM mode? if enter DCM mode, whether the peak inductor  current  damages the MOSFET?

    looking forward to your reply

  • Hi Sir

    The answer to your question is .... it depends!  In the article above I have tried to suggest a few different steps to mitigate each undesired ripple component.  The step which is best in each case depends on the limitations within which you are working.  Are you trying to achieve the smallest possible solution, or the most cost effective solution, or the most efficient solution?  For example, a fully shielded inductor will allow a very small layout but will cost more; a lower cost, non-shielded inductor can be fine if the output capacitors are further away but this is a larger solution; or slowing down the switching edges can help but this sacrifices a little efficiency.  The double sided layout described in this apps note (www.ti.com/.../slva630a.pdf) can certainly help in some cases.  Generally, I would say that time spent optimising the layout of your design is never wasted.  It will allow you to achieve the full potential of the devices and components chosen, but it can't really compensate for a poor component.