What’s not in the power MOSFET data sheet part 2: voltage-dependent leakage currents

Other Parts Discussed in Post: CSD15380F3

In part 1 of this series, I reviewed power metal-oxide semiconductor field-effect transistor (MOSFET) data sheets and explained what’s in the data sheet and more importantly, what’s not, while specifically looking at the temperature dependence of some key MOSFET parameters. In part 2, I’ll focus on voltage-dependent leakage currents – the drain-to-source leakage (IDSS) and the gate-to-source leakage (IGSS).

Why leakage currents? There are two fundamental reasons why leakage currents are important when selecting a power MOSFET for your application. First, in electronic systems, there is a green campaign to reduce wasted power, especially when the system is operating in standby mode. And second, in battery-operated systems low leakage helps maximize both battery life for primary cells and the run time between charges for secondary cells.

MOSFET leakage currents

As shown in Figure 1, the MOSFET data sheet for the CSD15380F3 specifies two leakage currents: IDSS and IGSS.


Figure 1: Leakage current specifications from the CSD15380F3 data sheet

The maximum leakage is specified at one voltage: IDSS at 80% of BVDSS (VGS = 0 V) and IGSS at the absolute maximum VGS (VDS = 0 V). I’m often asked how these parameters vary with voltage, and the answer depends not only on the applied voltage but also on the gate electrostatic discharge (ESD) structure, as detailed in the technical article, What type of ESD protection does your MOSFET include?” As a refresher, the three types of ESD protection used in TI MOSFETs are none (lowest leakage), single-ended (lowest leakage) and back-to-back (highest leakage).

IGSS current

In this section, I’ll present graphs showing IGSS variation with voltage for several TI N- and P-channel NexFETTm power MOSFETs with the three types of gate ESD protection. These are typical curves for design guidance only and not a guarantee of performance. TI only guarantees leakage as specified in the MOSFET data sheet.

Figure 2 shows sweeps of IGSS vs. VGS for a 30-V N-channel FET (NFET) and a –20-V P-channel FET (PFET) that have no gate ESD protection. The leakage is relatively flat until VGS gets close to its positive and negative absolute maximum limits.

Figure 2: IGSS vs. VGS with no ESD protection: 30-V NFET (a); and –20-V PFET (b)

Figure 3 shows IGSS for a 20-V N-channel FET and a –20-V P-channel FET with a single-ended gate ESD protection structure. The leakage current increases exponentially when the gate ESD diode becomes forward-biased. If this is likely to occur in an application, then you must use an external gate resistor to limit the current and prevent damage to the MOSFET.

  Figure 3: IGSS vs. VGS with single-ended ESD protection: 20-V NFET (a); and –20-V PFET (b)

The plots in Figure 4 display IGSS for a 60-V NFET and a –8-V PFET with a back-to-back gate ESD protection structure. These devices display a symmetric leakage characteristic around VGS = 0 V because of the back-to-back gate ESD diodes.


   Figure 4: IGSS vs. VGS with back-to-back ESD protection: 60-V NFET (a); and –8-V PFET (b)

IDSS current

The other MOSFET leakage current, IDSS, is from drain-to-source when the FET is off. The next several graphs show IDSS vs. VDS for TI NFETs and PFETs with the three types of ESD protection. These are typical curves for design guidance only and not a guarantee of performance. TI only guarantees leakage as specified in the MOSFET data sheet.

Figure 5 plots IDSS for a 30-V NFET and a –20-V PFET with no ESD protection.

Figure 5: IDSS vs. VDS with no ESD protection: 30-V NFET (a); and –20-V PFET (b)

Figure 6 shows IDSS for a 20-V N-channel MOSFET and a –20-V P-channel FET, with a single-ended gate ESD protection diode.

Figure 6: IDSS vs. VDS with single-ended ESD protection: 20-V NFET (a); and –20-V PFET (b)

The plots in Figure 7 display IDSS for a 12-V N-channel MOSFET and a –20-V P-channel MOSFET with the back-to-back gate ESD protection structure.

Figure 7: IDSS vs. VDS with back-to-back ESD protection: 12-V NFET (a); and –20-V PFET (b)

Conclusion

I hope that the typical curves of IGSS current and IGSS vs. VGS, and IDSS current and IDSS vs. VDS will help you understand how MOSFET leakage currents vary with voltage. TI specifies and tests the maximum leakage currents at the conditions in the Electrical Characteristics data sheet. As a reminder, always use the data-sheet limits when designing with TI FETs, and if you don’t see it in the data sheet, request it from your FET vendor.

Additional resources

Anonymous
  • Thanks for your feedback Sky Moon. I did not intend for this information to be very complex. The graphs presented in this article are to show general trends for leakage current versus voltage for the 3 types of gate ESD structures implemented in TI FETs. I often get questions from customers about how the leakage behaves at different conditions other than those specified in the FET datasheet. Hopefully, you will find this helpful. Best of luck in your future endeavors!

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