I was at a birthday party a few weeks ago and a guest I never met before asked me about my latest project at work. Immediately, I replied that I was working on a sequencing problem.
The funny part is he automatically thought that I was in the pharmaceutical business! To me, power supply sequencing sounds much more interesting than DNA sequencing, and it is definitely less complicated. Note to self – I need to be more specific.
Figure 1 - Flexible power up/down sequencing
The problem was to have the highest voltage rail to power-up first, and the next lower voltage rail to power up afterwards until all 4 voltages were powered. Then, each rail needed to be powered down in the reverse order. Implementing a power sequencing scheme is good design practice (see Figure 1) with any point-of-load power supply architecture that ultimately helped me solve my design problems. When all voltage rails of a system turn on suddenly, the primary power supply experiences a large demand at once and must accommodate any inrush currents from all rails. Accommodating these inrush currents increases the size of the power supply design and may cause a nuisance shut-down if not properly considered. Many performance DSPs and FPGAs require a specific sequencing scheme as a precautionary measure to improve long term reliability. There are many good resources available demonstrating power sequencing techniques. Read “Power Supply Sequencing for FPGAs” to understand the various power supply sequencing techniques such as cascading the power good into the enable pin, using reset ICs or implementing an analog or digital sequencer/monitor.
Cascading the power-good pin from a DC/DC converter into another converter’s enable pin is the easiest power supply sequencing method, but it is difficult to design for power-down. A reset IC is a good choice if the DC/DC converter doesn’t have a power good pin, but again power down is difficult. Analog and digital sequencers offer much more flexibility. Digital solutions offer a PMBus™ interface and many integrate monitoring. Ultimately, the best solution depends on specifications and complexity of the system. Performance processors, for example, clearly specify their sequencing requirements in the datasheets.
Figure 2 – 2 or 4 channel synchronous buck converter with PMBus interface
The solution I ended up using to solve my sequencing problem was TI’s 18V TPS65400 multi-channel synchronous buck converter (see Figure 2). The PMBus / I2C interface supported a turn-on and turn-off sequencing order that matched my requirements and even supported selectable delay times. The new device is configurable for either four, or two outputs using current sharing and provides flexibility for many sequencing schemes via the digital interface with the “Sequence Order” command. .
Have you experienced any sequencing problems recently? I mean, of course, power supply sequencing.