Power House - All Comments

RE: Power Tips: Multiply your output voltage

1597892 — Mon, 17 Jul 2017 04:53:00 GMT

Can an external current source be added to the 40 VDC output of a CW voltage multiplier so that it can be used as the 5% "on" pulsed input to a high Q resonant tank circuit?

RE: How to control turn on/off thresholds in voltage regulators using a logic level UVLO

1881345 — Tue, 27 Jun 2017 01:12:19 GMT

Nadav

The value of the Zener should be chosen close to the point you wish the UVLO to trip.

Resistor RT is used to adjust the trip point; I would start with a 10K or so.

Resistor RH is used to adjust the hysteresis of the trip point; I would use a 100K or 1Meg to start with.

This circuit is experimental, so feel free to adjust the component values until you arrive at a response that

works for you.

RE: How to control turn on/off thresholds in voltage regulators using a logic level UVLO

4687533 — Fri, 23 Jun 2017 06:40:44 GMT

Hi,

Thanks for a great post!

I'd like to build and test the uvlo circuits suggested above, however, some of the parts in the schematics don't have values, namely: RH, RT & the Zener diode.

Could you please clarify what are the values of these parts?

Also, how precise do the resistors in the circuits need to be (1%, 5%, etc.)?

Many thanks in advance.

RE: Power Tips: How to measure current – Part I

145069 — Wed, 21 Jun 2017 22:12:54 GMT

Hi Kamlesh,

It sounds like you have a signal to noise ratio problem. With 1:200 turns ratio, that means 2A = 10mA, depending on the resistor you are using the signal may be too small for what you are comparing it against. Also you might have problems with switching noise causing issues with the measurement. Hope this helps.

Thanks,

Robert

RE: Power Tips: How to measure current – Part I

3609598 — Wed, 21 Jun 2017 22:04:54 GMT

Sir,

I am trying to regulate current in Buck converter for battery charging application. Current is sensed using current transformer in series with Buck MOSFET and diode. Even though current is regulated up to 10A, I am finding difficult to regulate current less than 2A as CT is not correctly refleting MOSFET current. I am using tape wound core with 1:200 turns and switching frequency is 30kHz

Thanks

RE: Small and efficient power supply for the Altera™ MAX® 10 FPGA

1090425 — Wed, 24 May 2017 05:37:32 GMT

Great! What input voltage do you have in your typical system? Will this design fit?

RE: Small and efficient power supply for the Altera™ MAX® 10 FPGA

1266299 — Wed, 24 May 2017 03:50:04 GMT

Thanks Chris! That makes complete sense. My last MAX10 design used another vendor's regulators, but they are fairly expensive. I'm using the TPS65265 in a design for Xilinx Artix 7, but now I'll evaluate doing something similar to this reference design.

RE: Small and efficient power supply for the Altera™ MAX® 10 FPGA

1090425 — Sat, 13 May 2017 07:48:13 GMT

There are always multiple solutions to any given problem. The 'PMIC vs. discrete' discussion is a good example. Some applications demand a PMIC, while others refuse a PMIC.

I think the TPS65265 will be larger. The 5x5 size is larger than the sum of the 3 ICs used in this reference design. As well, external compensation is required--this is a lot of Rs and Cs. Finally, the typical switching frequency is lower which necessitates a larger output filter.

And a 17Vin capable device is not optimized to a 5V input, like this reference design. Efficiency will be lower.

Do you have a specific design for the MAX10 you are working on? There are other power solutions, besides this reference design.

RE: Small and efficient power supply for the Altera™ MAX® 10 FPGA

1266299 — Sat, 13 May 2017 03:04:36 GMT

Wouldn't a single TI TPS65265 triple buck regulator provide a smaller and more cost-effective solution?

RE: Waveform audit: my boost converter has an off-ramp!

4959843 — Tue, 09 May 2017 20:29:25 GMT

I believe your labels of Ton and Toff on the o'scope captures are incorrect. During Ton, Q1 is on so the switch node voltage is ta GND. During Toff, Q1 is off and the inductor conducts through D1 to the output so the switch node is at Vout + the foward drop of D1. Of course from the perspective of Q2 Ton and Toff are reversed but then it is a buck converter not the boot converter advertised in the title.

RE: Predicting output-capacitor ripple in a CCM boost PFC circuit

4861185 — Thu, 04 May 2017 17:23:09 GMT

Mr. Collin,

That was a dumb question :( !!!! I thought it was Itot^2 = I_lf^2 - I_hf^2. I should be careful while reading next time :(.

Thank you,

Abdelmouneim.

RE: Predicting output-capacitor ripple in a CCM boost PFC circuit

1139376 — Thu, 04 May 2017 13:38:21 GMT

Thanks for the feedback. The two equations are equivalent - they are just re-arrangements of each other. The relationship is that Itot^2 = I_lf^2 + I_hf^2

Regards

Colin

RE: Predicting output-capacitor ripple in a CCM boost PFC circuit

4861185 — Thu, 04 May 2017 01:10:34 GMT

Dear TI Member,

Thank you for the details provided in this article. This helps a lot in predicting the ac ripple in CCM boost PFCs.

I only have a comment regarding the equation (6): I was checking the same formula in www.ti.com/.../ucc28180.pdf equation (66) in which the total output capacitor current ripple is calculated as: the "SUM" or contribution of the two components [two line frequency and high frequency]. Whereas, in here, the total ripple is calculated as the "SUBTRACTION" of the two components.!!

Could you please explain this difference between the two equations!

Thank you,

Abdelmouneim.

RE: Design your power stage quite conveniently

1417166 — Wed, 08 Mar 2017 21:02:13 GMT

Agreed that this is a great tool, and the two accompanying documents are very useful. However, what would be REALLY useful is a table showing all the pros and cons of the different topologies. Nowhere can I see it mentioned what the benefits or pitfalls of the different designs are - where do you start?

Hopefully the Document authors will publish a table soon ... :-)

RE: Gate drive transformer vs. high/low side driver: Which way to go for power supply design?

4682211 — Mon, 06 Mar 2017 13:32:15 GMT

Good post. The gate-drive transformer can deliver both the logic gate-drive signal and required gate driver required peak current/power capability.