I hope you were sufficiently inspired by last week’s discussion on preventing electrostatic discharge (ESD)-related fails to check your PCB and make sure you aren’t guilty of making a board with ESD ‘hot-spots’. This week we will get into the details and good practices for PCB design.
When it comes to a good, robust PCB layout, the devil (as they say) is in the details. Keep in mind that ESD safety is only one piece of the puzzle. A well planned design should not only be able to provide safety against an ESD strike but also provide good signal and power integrity for the whole system. With this is mind I’ve laid out ideas not only for ESD-robustness but also for reducing noise emissions, coupled noise and maintaining signal and power integrity on the PCB.
A typical PCB layout process works similar to the process outlined in the figure.
When doing the initial PCB layout, here is a basic checklist of items that you need to think about:
Identify critical areas: When trying to identify sensitive areas, it is important to looks for signals that are the most susceptible to coupling in ESD from an external source or through a path in the larger system. Identifying the critical signals and nets helps focus on specific areas to ensure best signal integrity. An example of this would be a reset line that feeds to the reset pin of an MCU. On the PCB, this signal should be routed further away from transmit or receive lines to prevent crosstalk or noise from being coupled in due to proximity.
PCB floor-planning: Once the system’s critical paths and signals are well understood, it is important to think about how you will partition the PCB. For complex systems this is usually done by function. Clocking, analog, MCU, and power management are examples of functions where components are grouped together ensuring that the larger, more complex, system is split into smaller sub-systems. Remember (a) any components that support a high switching frequency need to be located away from slower logic and especially from analog; (b) try and keep analog and digital routing clean and separate; (c) when zones needs to interact with each other, think about the noise source in each zone and if a filtering mechanism is needed; (d) keep traces of critical signals as short as possible.
PCB layering: In most cases, complex systems mandate multi-layer PCBs. At the very least, the ground and power planes necessitate the allocation of two layers. Ground and power planes provide a fair amount of reduction in radiated emissions as well.
Minimizing crosstalk: When traces run parallel, signals can couple causing unwanted interference. Increasing the distance between parallel traces minimizes crosstalk. Try to alternate signals between different layers on the PCB and reduce the length of the sections where the traces run parallel.
Watch the clock: Clocking is one of the most critical aspects of a system. It is also one of the most susceptible to ESD-type failures. When using an external oscillator-based design, place the oscillator close to the MCU so the signal traces can be short. Ensure that clock traces have an unbroken reference ground plane. If you must use an external clock source, use one that has its own supply and ground. Since noise is a common cause of oscillator failures, it is important to identify the noise source and isolate it from the clock routing.
Using external components: Almost all EVMs TI builds with MSP430 MCUs use some form of ESD protection via external components. Take the MSP430FR5739 FRAM Experimenter’s Board as an example. If you pull up the schematics, you can see that the ESD protection device (TPD2E001) is placed right next to the mini-USB connector to minimize ESD coupling via the connector when a user plugs in the board. In devices with high speed interfaces like HDMI you can usually see more ‘heavy-duty’ protection devices especially close to the connectors. TI has a catalog of products for providing ESD protection for various interfaces which can help you find one suitable for your application.
The next time you start working on a project, make a checklist of things that you need to work through to make your device more robust against ESD. Check out the application report on System-Level ESD Design for some cool tips.
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