PLL Synthesizers: A brief overview.

One of the critical blocks in any wireless transceivers is a phase lock loop (PLL) synthesizer. A PLL is a versatile device that finds applications in signal synthesis, synchronization, modulation, demodulation, signal tracking, etc. A basic block diagram of a PLL synthesizer is shown in Figure 1.

Figure 1: Basic PLL synthesizer block diagram.

PLL synthesizers generate a radio frequency signal (FRF) from a fixed reference signal (FREF). It uses voltage controlled oscillator (VCO) that generates unstable FRF. VCO is one of the blocks that set synthesizers phase noise performance. PLL stabilizes FRF by synchronizing it with FREF. FRF can be adjusted by changing programmable feedback divider (DIV) divisor (N). DIV generates comparison frequency (FRF/N) using input FRF. Phase frequency detector (PFD), which serves as an error amplifier in the feedback loop, compares the phase/frequency of two inputs FREF and FRF/N. PFD minimizes the phase difference between these inputs. When FRF/N equals FREF the loop is termed, locked resulting equation (1).

FRF = N. FREF               (1)

Generally, crystal oscillators are used to generate FREF which have accuracy ranging from 5 to 50 ppm. When the PLL is locked, accuracy of FRF will be the same as FREF. Depending on the applications channel spacing (frequency resolution), the divider can be programmed as integer (integer-N PLL) or non-integer (Fractional –N PLL) division ratio. For the integer values of N, the minimum channel spacing is FREF, thus to obtain smaller spacing FREF has to be small which leads large N. A large value of N results in increased in-band phase noise of VCO by 20log(N). Fractional-N PLL can provide the lowest possible channel spacing with frequency resolution in order of Hz but also generate unwanted fractional spurs. Signals from PFD followed by charge pump (CP) are filtered through a low pass filter (LPF).

LPF rejects noise and undesired high frequency components on VCO control voltage that could degrade its phase noise performance. Smaller LPF loop bandwidth results in better phase noise and spurious performance but slower lock time. Whereas, larger loop bandwidth provides faster lock time but less spurious rejection. As per applications requirements LPF can be designed using external passive components or incorporated within silicon. TRF3720, a high-performance fully integrated I/Q modulator and PLL synthesizer, uses an external loop filter giving base station customers flexibility to design an application specific loop filter. It exhibits wide 300-MHz to 4800-MHz tuning range and a -132 dBc/Hz phase noise at 1-MHz offset of VCO frequency 2300-MHz, enabling it to meet the stringent wireless infrastructure standards.

Applications such as battery powered consumer electronics, low-power wireless sensors, home automation systems and remote controls, where low cost, low power, less board of materials (BOM) and smaller size are highly desired, generally use digitally designed PLL synthesizer blocks with an on-chip integrated loop filter. This is termed as an all-digital phase lock loop (ADPLL). A basic block diagram of ADPLL synthesizer is shown in Figure 2.

Figure 2: Basic ADPLL synthesizer block diagram.

In ADPLL, PFD and charge pump are replaced with time to digital converter (TDC) and digital phase detector (PD). VCO is replaced with a digitally controlled oscillator (DCO) and the analog low pass filter is replaced with a digital low pass filter. Loop bandwidth of ADPLL can be dynamically changed during locking enabling better phase noise, lower spurious performance as well as faster lock time. Additionally, ADPLL also has the capability of direct frequency modulation generating modulated FRF. CC2560 is a single-chip low power, less BOM, Bluetooth solution that incorporates an ADPLL and provides best in class RF performance.