A Conversation with TI’s ESD Guru

Other Parts Discussed in Post: STRIKE

Last week we looked at demystifying ESD testing terminology. This week I had the chance to sit down and talk with Zeb Agha, an ESD Guru at TI with seven years of experience in solving customer’s ESD-related issues. He brought up some common things to look for if you suspect your application is the victim of an ESD-related failure.  

(1) How did the failure manifest? There are multiple ways in which an ESD failure might manifest, for example hard, soft or latent failures. If a hard or non-recoverable fail is observed, a device on the board that is subject to ESD testing is permanently damaged. This can be verified by performing a failure analysis and observing the damage optically or via under a scanning electron microscope (SEM). Boards or devices that are sent back to the manufacturer for failure analysis routinely undergo such testing. Soft failures can manifest as latch-up of specific pins that couple ESD/EMI through conduction or radiation. Latent failures may not show any external symptoms of failure but damage device reliability or reduce the MTBF factor.

(2) What caused the failure? If you have an ESD expert at hand he will most likely be able to look at your board and point out weaknesses and areas of ESD susceptibility with a visual inspection. Is there an unshielded cable that leads from an external interface back to the board? Does the PCB support an independent ground layer? Are there any protection devices next to ESD hot-spots such as a USB connector? If debugging a suspected ESD fail on an MCU and it is a soft failure, we can gain some information by reading the state of the registers when the failure occurred. For example, if the board suddenly seems to stop functioning and a reset of the MCU brings the board back up, reading state registers, program counters etc can provide valuable information on the state of the device at the time of failure. This can be implemented by simple means such as a serial output stream via the UART or using a state trace mechanism via the debugger.

(3) Are there any hot-spots? IEC testing mandates that if the user has an interaction with the PCB such as through a switch, the testing must use contact discharge i.e. the ESD voltage is discharged by touching the external interface directly. In such cases where certain areas in the PCB are known to have increased exposure or higher susceptibility it is important to build in protection via external ESD-protection diodes such as the TPD2E001  a single chip ESD protection array for high-speed data interfaces.

A white paper by Roger Liang, Systems Engineer for the Integrated Protection Devices (IPD) group in TI also highlights a class of protection devices called Transient Voltage Suppressors (TVS). TVSs are placed on general purpose I/Os that are exposed to the possibility of a strike. Under normal operating conditions these devices are open and do not interfere with the GPIO operation. In the event of an ESD strike, the TVS device forms a short circuit path to ground to safely discharge the excess voltage. For more details on how TVSs work and information on system=level ESD design refer to Design considerations for system-level ESD circuit protection.  For a comprehensive list of ESD protection devices, visit the IPD group’s web page or browse through their brochure and select a device that fits your applications needs.

Remember that when an ESD-related failure occurs, it is important to walk through the exact scenario leading up to and after the ESD strike to determine how to prevent or protect the application from future ESD events.

In my next blog post I will discuss some common pitfalls that lead to lowered ESD resistance as well as measures to combat strikes and increase the possibility of passing system-level testing.

Stay tuned.